| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1053 Words[IdxW].push_back(HiHalf(W0, DAG)); in createHvxPrefixPred()
1063 Words[IdxW].push_back(HiHalf(T, DAG)); in createHvxPrefixPred()
1391 V1 = HiHalf(VecV, DAG); in insertHvxSubvectorReg()
1438 SDValue R1 = HiHalf(V, DAG); in insertHvxSubvectorReg()
2559 {HiHalf(P2, DAG), LoHalf(P1, DAG), S16}, DAG); in emitHvxMulHsV60()
2607 {HiHalf(P1, DAG), LoHalf(P1, DAG)}, DAG); in emitHvxMulLoHiV60()
2615 {HiHalf(P2, DAG), T3, S16}, DAG); in emitHvxMulLoHiV60()
2620 Hi = DAG.getNode(ISD::ADD, dl, VecTy, {HiHalf(P0, DAG), T4}); in emitHvxMulLoHiV60()
2666 SDValue Hi = HiHalf(P1, DAG); in emitHvxMulLoHiV62()
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| H A D | HexagonISelDAGToDAGHVX.cpp | 631 return OpRef(R.OpN & (Undef | Index | HiHalf)); in hi()
648 HiHalf = 0x40000000, enumerator
649 Whole = LoHalf | HiHalf,
724 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf); in print()
1185 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf); in materialize()
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| H A D | HexagonISelLowering.h | 483 SDValue HiHalf(SDValue V, SelectionDAG &DAG) const { in HiHalf() function
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| H A D | HexagonISelLowering.cpp | 2720 ExtV = Off == 0 ? LoHalf(VecV, DAG) : HiHalf(VecV, DAG); in extractVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 2031 MachineInstr *HiHalf = in computeBase() local
2038 (void)HiHalf; in computeBase()
2039 LLVM_DEBUG(dbgs() << " "; HiHalf->dump();); in computeBase()
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| H A D | SIInstrInfo.cpp | 8301 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp() local
8316 Worklist.insert(&HiHalf); in splitScalar64BitUnaryOp()
8408 MachineInstr *HiHalf = in splitScalarSMulU64() local
8428 legalizeOperands(*HiHalf, MDT); in splitScalarSMulU64()
8474 MachineInstr *HiHalf = in splitScalarSMulPseudo() local
8492 legalizeOperands(*HiHalf, MDT); in splitScalarSMulPseudo()
8546 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp() local
8560 Worklist.insert(&HiHalf); in splitScalar64BitBinaryOp()
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| H A D | SIISelLowering.cpp | 5442 MachineInstr *HiHalf = in EmitInstrWithCustomInserter() local
5456 TII->legalizeOperands(*HiHalf); in EmitInstrWithCustomInserter()
7757 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
7761 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf); in lowerINSERT_VECTOR_ELT()
7773 InsertLo ? DAG.getBuildVector(MVT::v2i32, SL, {InsHalf, HiHalf}) in lowerINSERT_VECTOR_ELT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 5046 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D() local
5063 .addDef(HiHalf) in emitLDR_D()
5071 .addUse(HiHalf); in emitLDR_D()
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