| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 120 void HexagonInstrInfo::anchor() {} in anchor()
122 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) in HexagonInstrInfo() function in HexagonInstrInfo
156 bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const { in isAsCheapAsAMove()
187 bool HexagonInstrInfo::shouldSink(const MachineInstr &MI) const { in shouldSink()
199 MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB, in findLoopInstr()
290 Register HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
338 Register HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()
388 bool HexagonInstrInfo::hasLoadFromStackSlot( in hasLoadFromStackSlot()
406 bool HexagonInstrInfo::hasStoreToStackSlot( in hasStoreToStackSlot()
436 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, in analyzeBranch()
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| H A D | HexagonFrameLowering.h | 24 class HexagonInstrInfo; variable
120 void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
137 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
140 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
143 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
146 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
149 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
152 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
155 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
158 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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| H A D | HexagonBitTracker.h | 18 class HexagonInstrInfo; variable
32 const HexagonInstrInfo &tii, MachineFunction &mf);
48 const HexagonInstrInfo &TII;
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| H A D | HexagonHazardRecognizer.h | 24 const HexagonInstrInfo *TII;
49 const HexagonInstrInfo *HII, in HexagonHazardRecognizer()
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| H A D | HexagonSubtarget.h | 87 bool shouldTFRICallBind(const HexagonInstrInfo &HII,
103 HexagonInstrInfo InstrInfo;
124 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
353 bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
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| H A D | HexagonVLIWPacketizer.h | 19 class HexagonInstrInfo; variable
76 const HexagonInstrInfo *HII;
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| H A D | HexagonFixupHwLoops.cpp | 112 const HexagonInstrInfo *HII = in fixupLoopInstrs()
113 static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in fixupLoopInstrs()
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| H A D | HexagonSubtarget.cpp | 265 auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII); in apply()
299 const HexagonInstrInfo &HII, const SUnit &Inst1, in shouldTFRICallBind()
382 const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII); in apply()
444 const HexagonInstrInfo *QII = getInstrInfo(); in adjustSchedDependency()
547 auto &QII = static_cast<const HexagonInstrInfo &>(*getInstrInfo()); in updateLatency()
633 const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc, in isBestZeroLatency()
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| H A D | HexagonNewValueJump.cpp | 95 const HexagonInstrInfo *QII;
116 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, in INITIALIZE_PASS_DEPENDENCY()
237 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, in canCompareBeNewValueJump()
459 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| H A D | HexagonVectorPrint.cpp | 54 const HexagonInstrInfo *QII = nullptr;
98 const DebugLoc &DL, const HexagonInstrInfo *QII, in addAsmInstr()
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| H A D | HexagonISelDAGToDAG.h | 25 class HexagonInstrInfo; variable
30 const HexagonInstrInfo *HII;
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| H A D | HexagonPeephole.cpp | 82 const HexagonInstrInfo *QII;
113 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| H A D | HexagonMachineScheduler.cpp | 28 const auto *QII = static_cast<const HexagonInstrInfo *>(TII); in hasDependence()
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| H A D | HexagonInstrInfo.h | 38 class HexagonInstrInfo : public HexagonGenInstrInfo {
48 explicit HexagonInstrInfo(HexagonSubtarget &ST);
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| H A D | HexagonBitSimplify.cpp | 252 uint16_t Begin, const HexagonInstrInfo &HII);
652 BitVector &Bits, uint16_t Begin, const HexagonInstrInfo &HII) { in getUsedBits()
995 const HexagonInstrInfo &HII;
1081 RedundantInstrElimination(BitTracker &bt, const HexagonInstrInfo &hii, in RedundantInstrElimination()
1097 const HexagonInstrInfo &HII;
1403 ConstGeneration(BitTracker &bt, const HexagonInstrInfo &hii, in ConstGeneration()
1415 const HexagonInstrInfo &HII;
1534 CopyGeneration(BitTracker &bt, const HexagonInstrInfo &hii, in CopyGeneration()
1544 const HexagonInstrInfo &HII;
1776 const HexagonInstrInfo &hii, const HexagonRegisterInfo &hri, in BitSimplification()
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| H A D | HexagonBranchRelaxation.cpp | 69 const HexagonInstrInfo *HII;
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| H A D | HexagonLoopAlign.cpp | 65 const HexagonInstrInfo *HII = nullptr;
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| H A D | HexagonFrameLowering.cpp | 1720 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const { in expandCopy()
1741 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const { in expandStoreInt()
1774 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const { in expandLoadInt()
1805 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const { in expandStoreVecPred()
1842 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const { in expandLoadVecPred()
1877 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const { in expandStoreVec2()
1937 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const { in expandLoadVec2()
1978 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const { in expandStoreVec()
2007 const HexagonInstrInfo &HII, SmallVectorImpl<Register> &NewRegs) const { in expandLoadVec()
2488 const HexagonInstrInfo &HII, Register SP, unsigned CF) const { in expandAlloca()
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| H A D | HexagonVLIWPacketizer.cpp | 116 const HexagonInstrInfo *HII = nullptr;
568 const HexagonInstrInfo *HII) { in getPredicateSense()
577 const HexagonInstrInfo *HII) { in getPostIncrementOperand()
950 const HexagonInstrInfo *QII) { in getPredicatedRegister()
1107 const HexagonInstrInfo &HII) { in cannotCoexistAsymm()
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| H A D | HexagonGenMemAbsolute.cpp | 43 const HexagonInstrInfo *TII;
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| H A D | HexagonVExtract.cpp | 55 const HexagonInstrInfo *HII = nullptr;
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| H A D | HexagonCopyToCombine.cpp | 60 const HexagonInstrInfo *TII;
125 static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII, in isCombinableInstType()
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| H A D | HexagonTfrCleanup.cpp | 67 const HexagonInstrInfo *HII;
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| H A D | Hexagon.td | 392 def HexagonInstrInfo : InstrInfo;
502 let InstructionSet = HexagonInstrInfo;
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| H A D | HexagonGenMux.cpp | 88 const HexagonInstrInfo *HII = nullptr;
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