120 void HexagonInstrInfo::anchor() {}  in anchor()
122 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)  in HexagonInstrInfo()  function in HexagonInstrInfo
156 bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {  in isAsCheapAsAMove()
187 bool HexagonInstrInfo::shouldSink(const MachineInstr &MI) const {  in shouldSink()
199 MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB,  in findLoopInstr()
290 Register HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,  in isLoadFromStackSlot()
338 Register HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,  in isStoreToStackSlot()
388 bool HexagonInstrInfo::hasLoadFromStackSlot(  in hasLoadFromStackSlot()
406 bool HexagonInstrInfo::hasStoreToStackSlot(  in hasStoreToStackSlot()
436 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,  in analyzeBranch()
606 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,  in removeBranch()
629 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,  in insertBranch()
732   const HexagonInstrInfo *TII;
806 HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {  in analyzeLoopForPipelining()
820 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,  in isProfitableToIfCvt()
826 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,  in isProfitableToIfCvt()
833 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,  in isProfitableToDupForIfCvt()
857 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,  in copyPhysReg()
958 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,  in storeRegToStackSlot()
1006 void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,  in loadRegFromStackSlot()
1052 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
1546 HexagonInstrInfo::expandVGatherPseudo(MachineInstr &MI) const {  in expandVGatherPseudo()
1634 bool HexagonInstrInfo::reverseBranchCondition(  in reverseBranchCondition()
1649 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,  in insertNoop()
1655 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {  in isPostIncrement()
1667 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {  in isPredicated()
1672 bool HexagonInstrInfo::PredicateInstruction(  in PredicateInstruction()
1724 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,  in SubsumesPredicate()
1730 bool HexagonInstrInfo::ClobbersPredicate(MachineInstr &MI,  in ClobbersPredicate()
1757 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {  in isPredicable()
1793 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,  in isSchedulingBoundary()
1841 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,  in getInlineAsmLength()
1869 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(  in CreateTargetPostRAHazardRecognizer()
1880 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,  in analyzeCompare()
1970 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()
1976 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(  in CreateTargetScheduleState()
1986 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(  in areMemAccessesTriviallyDisjoint()
2044 bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,  in getIncrementValue()
2067 HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
2073 HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {  in getSerializableDirectMachineOperandTargetFlags()
2092 HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {  in getSerializableBitmaskMachineOperandTargetFlags()
2101 Register HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {  in createVR()
2118 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {  in isAbsoluteSet()
2122 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {  in isAccumulator()
2127 bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr &MI) const {  in isBaseImmOffset()
2131 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {  in isComplex()
2140 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {  in isCompoundBranchInstr()
2146 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {  in isConstExtended()
2195 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {  in isDeallocRet()
2210 bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,  in isDependent()
2241 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {  in isDotCurInst()
2252 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {  in isDotNewInst()
2260 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,  in isDuplexPair()
2267 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {  in isEndLoopN()
2272 bool HexagonInstrInfo::isExpr(unsigned OpType) const {  in isExpr()
2286 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {  in isExtendable()
2308 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {  in isExtended()
2321 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {  in isFloat()
2328 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,  in isHVXMemWithAIndirect()
2337 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {  in isIndirectCall()
2348 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {  in isIndirectL4Return()
2362 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {  in isJumpR()
2380 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,  in isJumpWithinBranchRange()
2422 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {  in isLateSourceInstr()
2428 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {  in isLoopN()
2440 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {  in isMemOp()
2472 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {  in isNewValue()
2477 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {  in isNewValue()
2482 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {  in isNewValueInst()
2486 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {  in isNewValueJump()
2490 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {  in isNewValueJump()
2494 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {  in isNewValueStore()
2499 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {  in isNewValueStore()
2505 bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,  in isOperandExtended()
2512 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {  in isPredicatedNew()
2518 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {  in isPredicatedNew()
2524 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {  in isPredicatedTrue()
2530 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {  in isPredicatedTrue()
2538 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {  in isPredicated()
2543 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {  in isPredicateLate()
2548 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {  in isPredictedTaken()
2555 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {  in isSaveCalleeSavedRegsCall()
2562 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {  in isSignExtendingLoad()
2640 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {  in isSolo()
2645 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {  in isSpillPredRegOp()
2655 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {  in isTailCall()
2666 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {  in isTC1()
2671 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {  in isTC2()
2676 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {  in isTC2Early()
2681 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {  in isTC4x()
2687 bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,  in isToBeScheduledASAP()
2705 bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {  in isHVXVec()
2711 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {  in isValidAutoIncImm()
2748 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,  in isValidOffset()
2958 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {  in isVecAcc()
2962 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {  in isVecALU()
2970 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,  in isVecUsableNextPacket()
2984 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {  in isZeroExtendingLoad()
3063 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,  in addLatencyToSchedule()
3072 bool HexagonInstrInfo::getMemOperandsWithOffsetWidth(  in getMemOperandsWithOffsetWidth()
3085 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,  in canExecuteInBundle()
3110 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {  in doesNotReturn()
3115 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {  in hasEHLabel()
3124 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {  in hasNonExtEquivalent()
3159 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {  in hasPseudoInstrPair()
3164 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)  in hasUncondBranch()
3176 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {  in mayBeCurLoad()
3183 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {  in mayBeNewStore()
3191 bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,  in producesStall()
3209 bool HexagonInstrInfo::producesStall(const MachineInstr &MI,  in producesStall()
3229 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,  in predCanBeUsedAsDotNew()
3264 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {  in PredOpcodeHasJMP_c()
3275 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {  in predOpcodeHasNot()
3281 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {  in getAddrMode()
3291 HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,  in getBaseAndOffset()
3323 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,  in getBaseAndOffsetPosition()
3360 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(  in getBranchingInstrs()
3418 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {  in getCExtOpNum()
3425 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(  in getCompoundCandidateGroup()
3513 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,  in getCompoundOpcode()
3540 int HexagonInstrInfo::getDuplexOpcode(const MachineInstr &MI,  in getDuplexOpcode()
3597 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {  in getCondOpcode()
3609 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {  in getDotCurOp()
3629 int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {  in getNonDotCurOp()
3730 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {  in getDotNewOp()
3771 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,  in getDotNewPredJumpOp()
3857 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,  in getDotNewPredOp()
3872 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {  in getDotOldOp()
3923 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(  in getDuplexCandidateGroup()
4303 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {  in getEquivalentHWInstr()
4307 unsigned HexagonInstrInfo::getInstrTimingClassLatency(  in getInstrTimingClassLatency()
4327 std::optional<unsigned> HexagonInstrInfo::getOperandLatency(  in getOperandLatency()
4371 bool HexagonInstrInfo::getInvertedPredSense(  in getInvertedPredSense()
4380 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {  in getInvertedPredicatedOpcode()
4391 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {  in getMaxValue()
4405 bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {  in isAddrModeWithOffset()
4433 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const {  in isPureSlot0()
4445 bool HexagonInstrInfo::isRestrictNoSlot1Store(const MachineInstr &MI) const {  in isRestrictNoSlot1Store()
4451 void HexagonInstrInfo::changeDuplexOpcode(MachineBasicBlock::instr_iterator MII,  in changeDuplexOpcode()
4469 void HexagonInstrInfo::translateInstrsForDup(MachineFunction &MF,  in translateInstrsForDup()
4479 void HexagonInstrInfo::translateInstrsForDup(  in translateInstrsForDup()
4488 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {  in getMemAccessSize()
4511 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {  in getMinValue()
4525 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {  in getNonExtOpcode()
4549 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,  in getPredReg()
4569 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {  in getPseudoInstrPair()
4573 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {  in getRegForm()
4581 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {  in getSize()
4615 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {  in getType()
4620 InstrStage::FuncUnits HexagonInstrInfo::getUnits(const MachineInstr &MI) const {  in getUnits()
4628 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {  in nonDbgBBSize()
4632 unsigned HexagonInstrInfo::nonDbgBundleSize(  in nonDbgBundleSize()
4642 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {  in immediateExtend()
4655 bool HexagonInstrInfo::invertAndChangeJumpTarget(  in invertAndChangeJumpTarget()
4676 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {  in genAllInsnTimingClasses()
4698 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {  in reversePredSense()
4705 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {  in reversePrediction()
4716 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)  in validateBranchCond()
4721 void HexagonInstrInfo::
4731 bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {  in getBundleNoShuf()
4738 short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {  in changeAddrMode_abs_io()
4742 short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {  in changeAddrMode_io_abs()
4746 short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {  in changeAddrMode_io_pi()
4750 short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {  in changeAddrMode_io_rr()
4754 short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {  in changeAddrMode_pi_io()
4758 short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {  in changeAddrMode_rr_io()
4762 short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {  in changeAddrMode_rr_ur()
4766 short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {  in changeAddrMode_ur_rr()
4770 MCInst HexagonInstrInfo::getNop() const {  in getNop()