Searched refs:HAL_TXDESC_CTSENA (Results 1 – 6 of 6) sorted by relevance
273 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) in ath_tx_rate_fill_rcflags()883 (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) { in ath_tx_form_aggr()908 ~ (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA); in ath_tx_form_aggr()911 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA); in ath_tx_form_aggr()
1061 flags &= ~(HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA); in ath_tx_calc_protection()1079 flags |= HAL_TXDESC_CTSENA; in ath_tx_calc_protection()1268 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) { in ath_tx_set_rtscts()1796 flags &= ~(HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA); in ath_tx_normal_setup()2234 flags |= HAL_TXDESC_CTSENA; in ath_tx_raw_start()2264 flags &= ~(HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA); in ath_tx_raw_start()2281 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) in ath_tx_raw_start()
261 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ macro
336 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) in ar5416SetupTxDesc()405 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0) in ar5416SetupTxDesc()623 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) in ar5416SetupFirstTxDesc()658 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0) in ar5416SetupFirstTxDesc()888 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { in ar5416Set11nRateScenario()
703 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) in ar5212SetupTxDesc()749 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0) in ar5212SetupTxDesc()
731 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { in ar9300_set_11n_rate_scenario()