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Searched refs:GPRs (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td259 // GPRs without the PC. Some ARM instructions do not allow the PC in
271 // GPRs without the PC but with APSR. Some instructions allow accessing the
282 // GPRs without the SP register. Used for BXAUT and AUTG
292 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
339 // GPRs without the PC and SP but with APSR_NZCV.Some instructions allow
548 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
549 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
557 // Register class representing a pair of even-odd GPRs.
562 // Register class representing a pair of even-odd GPRs, except (R12, SP).
H A DARMCallingConv.td36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
133 // i64/f64 is passed in even pairs of GPRs
315 // Sometimes we need to split the push of the callee-saved GPRs into two
/freebsd/contrib/llvm-project/libunwind/src/
H A DRegisters.hpp97 struct GPRs { struct in libunwind::Registers_x86
116 GPRs _registers;
315 struct GPRs { struct in libunwind::Registers_x86_64
341 GPRs _registers;
1854 struct GPRs { struct in libunwind::Registers_arm64
1863 GPRs _registers;
1875 static_assert(sizeof(GPRs) == 0x110, in Registers_arm64()
1878 static_cast<const uint8_t *>(registers) + sizeof(GPRs), in Registers_arm64()
2166 struct GPRs { struct in libunwind::Registers_arm
2192 GPRs _registers;
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td211 // Even though 3 GPRs, 4 FPRs, and 8 VRs may be used,
214 // GPRs 1-3. FP values and vector-type arguments are instead passed in FPRs
227 // Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRs.
H A DSystemZFrameLowering.cpp1334 auto &GPRs = SystemZ::XPLINK64ArgGPRs; in emitPrologue() local
1339 unsigned Reg = GPRs[I]; in emitPrologue()
H A DSystemZInstrVector.td2205 // Moving 32-bit values between GPRs and FPRs can be done using VLVGF
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCGenRegisterBankInfo.def104 // GPRs, FPRs and vectors. It currently only handles bitcasting to
H A DPPCCallingConv.td115 // vectors within registers, as well as it handles the shadowing of GPRs
144 // Handle support for vector types, and shadow GPRs as necessary.
282 // in a GPR (or in the parameter list area if all GPRs are allocated) from the
H A DPPCISelLowering.cpp6884 const ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX() local
6904 unsigned NextReg = State.getFirstUnallocated(GPRs); in CC_AIX()
6905 while (NextReg != GPRs.size() && in CC_AIX()
6906 !isGPRShadowAligned(GPRs[NextReg], ObjAlign)) { in CC_AIX()
6908 MCRegister Reg = State.AllocateReg(GPRs); in CC_AIX()
6913 NextReg = State.getFirstUnallocated(GPRs); in CC_AIX()
6919 if (MCRegister Reg = State.AllocateReg(GPRs)) in CC_AIX()
6946 if (MCRegister Reg = State.AllocateReg(GPRs)) in CC_AIX()
6967 if (MCRegister Reg = State.AllocateReg(GPRs)) { in CC_AIX()
7019 unsigned NextRegIndex = State.getFirstUnallocated(GPRs); in CC_AIX()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td326 // Moves two GPRs to an FPR.
332 // Moves an FPR to two GPRs.
/freebsd/sys/contrib/device-tree/Bindings/powerpc/opal/
H A Dpower-mgt.txt46 0x00001000 /* Restore GPRs like nap */
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_cde.td60 // CX* instructions operating on GPRs
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td498 // Moves two GPRs to an FPR.
504 // Moves an FPR to two GPRs.
H A DRISCVFeatures.td78 : RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td652 // GPRs or on the stack.
1142 // GPRs are preserved.
1152 // All GPRs - except r11 and return registers.
H A DX86InstrOperands.td124 // GPRs available for tailcall.
H A DX86RegisterInfo.td586 // GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
596 // GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td335 def i64x8 : ValueType<512, 236>; // 8 Consecutive GPRs (AArch64)
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td261 // The first 4 MMX vector arguments are passed in GPRs.
H A DAArch64RegisterInfo.td850 // Armv8.7a accelerator extension register operands: 8 consecutive GPRs
H A DAArch64InstrInfo.td10395 // Custom DAG nodes and isel rules to make a 64-byte block out of eight GPRs,
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrInfo.td693 // To compare the contents of two GPRs.
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td2199 // their GPRs).