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Searched refs:GPR_64 (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td129 SLTI_FM<0xa>, GPR_64;
131 SLTI_FM<0xb>, GPR_64;
133 ADDI_FM<0xc>, GPR_64;
135 ADDI_FM<0xd>, GPR_64;
137 ADDI_FM<0xe>, GPR_64;
138 def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM, GPR_64;
154 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>, GPR_64;
155 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>, GPR_64;
157 GPR_64;
159 GPR_64;
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H A DMipsCondMov.td112 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
114 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
116 ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
124 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
126 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
128 ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
135 CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
142 CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
159 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;
162 INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;
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H A DMips64r6InstrInfo.td156 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
157 def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
168 def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64;
169 def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64;
171 def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64;
172 def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64;
173 def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64;
174 def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64;
175 def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64;
176 def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64;
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H A DMipsInstrFPU.td959 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64;
960 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64,
H A DMipsInstrInfo.td268 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86GenRegisterBankInfo.def65 INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64
H A DX86CallingConv.td43 list<Register> GPR_64 = [];
56 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
70 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];
109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
129 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
134 CCAssignToReg<RC.GPR_64>>>,
208 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
213 CCAssignToReg<RC.GPR_64>>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6863 static const MCPhysReg GPR_64[] = {// 64-bit registers. in CC_AIX() local
6872 const ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX()
7455 static const MCPhysReg GPR_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6, in LowerFormalArguments_AIX() local
7457 const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32); in LowerFormalArguments_AIX()
7467 IsPPC64 ? MF.addLiveIn(GPR_64[GPRIndex], &PPC::G8RCRegClass) in LowerFormalArguments_AIX()