Home
last modified time | relevance | path

Searched refs:GPRC (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZc.td107 : RVInst16CLB<funct6, 0b00, (outs GPRC:$rd),
117 DAGOperand rty = GPRC>
129 (ins GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
138 DAGOperand rty = GPRC>
149 RVInst16CU<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
285 def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
286 (C_MUL GPRC:$rs1, GPRC:$rs2)>;
288 def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
289 (C_MUL GPRC:$rs1, GPRC:$rs2)>;
293 def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1),
[all …]
H A DRISCVInstrInfoXwch.td64 def QK_C_LBU : RVInst16CL<0b001, 0b00, (outs GPRC:$rd),
75 (ins GPRC:$rs2, GPRCMem:$rs1,
86 def QK_C_LHU : RVInst16CL<0b001, 0b10, (outs GPRC:$rd),
96 (ins GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),
105 def QK_C_LBUSP : QKStackInst<0b00, (outs GPRC:$rd_rs2),
114 (ins GPRC:$rd_rs2, SPMem:$rs1,
123 def QK_C_LHUSP : QKStackInst<0b01, (outs GPRC:$rd_rs2),
133 (ins GPRC:$rd_rs2, SPMem:$rs1, uimm5_lsb0:$imm),
149 def : InstAlias<"qk.c.lbu $rd, (${rs1})", (QK_C_LBU GPRC:$rd, GPRCMem:$rs1, 0)>;
150 def : InstAlias<"qk.c.sb $rs2, (${rs1})", (QK_C_SB GPRC:$rs2, GPRCMem:$rs1, 0)>;
[all …]
H A DRISCVInstrInfoC.td261 : RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, bare_simm9_lsb0:$imm),
274 : RVInst16CB<0b100, 0b01, (outs GPRC:$rd),
275 (ins GPRC:$rs1, uimmlog2xlennonzero:$imm),
285 : RVInst16CA<funct6, funct2, 0b01, (outs GPRC:$rd_wb),
286 (ins GPRC:$rd, GPRC:$rs2), OpcodeStr, "$rd, $rs2"> {
299 def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
318 def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
346 def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
361 def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
389 def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
[all …]
H A DRISCVInstrInfoXqci.td584 : RVInst16CB<0b100, 0b01, (outs GPRC:$rd),
585 (ins GPRC:$rs1, uimmlog2xlennonzero:$shamt),
901 def QC_C_MULIADD : RVInst16CL<0b001, 0b10, (outs GPRC:$rd_wb),
902 (ins GPRC:$rd, GPRC:$rs1, uimm5:$uimm),
969 def QC_C_MVEQZ : RVInst16CL<0b101, 0b10, (outs GPRC:$rd_wb),
970 (ins GPRC:$rd, GPRC:$rs1),
1587 def : CompressPat<(QC_E_LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm),
1588 (C_LBU GPRC:$rd, GPRCMem:$rs1, uimm2:$imm)>;
1589 def : CompressPat<(QC_E_LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm),
1590 (C_LHU GPRC:$rd, GPRCMem:$rs1, uimm2_lsb0:$imm)>;
[all …]
H A DRISCVRegisterInfo.td89 // are not part of GPRC, the most restrictive register class used by the
286 def GPRC : GPRRegisterClass<(add (sequence "X%u", 10, 15),
H A DRISCVInstrInfo.td220 def GPRCMem : MemOperand<GPRC>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp761 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
762 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
827 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in prepareDynamicAlloca() local
868 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
876 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in prepareDynamicAlloca()
970 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
972 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
984 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
1015 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore() local
1017 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
[all …]
H A DPPCRegisterInfo.td334 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
342 let AltOrders = [(add (sub GPRC, R2), R2),
366 def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
535 def gprc : RegisterOperand<GPRC> {
613 def spe4rc : RegisterOperand<GPRC> {
H A DPPCISelLowering.cpp13093 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in EmitPartwordAtomicBinary() local
13096 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
13098 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
13099 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
13100 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
13101 Register Mask2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
13102 Register Mask3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
13103 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
13104 Register Tmp3Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
13105 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary()
[all …]
H A DPPCFrameLowering.cpp2307 const TargetRegisterClass &GPRC = PPC::GPRCRegClass; in addScavengingSpillSlot() local
2309 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
H A DPPCInstrVSX.td2669 (COPY_TO_REGCLASS (XVTDIVDP $A, $B), GPRC)>;
2671 (COPY_TO_REGCLASS (XVTDIVSP $A, $B), GPRC)>;
2673 (COPY_TO_REGCLASS (XVTSQRTDP $A), GPRC)>;
2675 (COPY_TO_REGCLASS (XVTSQRTSP $A), GPRC)>;