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Searched refs:GPR32RegClass (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp324 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
340 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
354 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
391 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP()
397 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); in materializeFP()
399 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); in materializeFP()
410 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
432 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
648 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
654 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
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H A DMipsInstructionSelector.cpp128 return &Mips::GPR32RegClass; in getRegClassForTypeOnBank()
168 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass); in materialize32BitImm()
367 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
375 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
383 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
395 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
475 Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
478 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
593 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
604 Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass); in select()
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H A DMipsMachineFunction.cpp52 return Mips::GPR32RegClass; in getGlobalBaseRegClass()
82 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
163 : Mips::GPR32RegClass; in createEhDataRegsFI()
175 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI()
H A DMipsOptionRecord.h47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
66 const MCRegisterClass *GPR32RegClass; variable
H A DMipsSEFrameLowering.cpp317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64()
385 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64()
422 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
590 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptPrologueStub()
719 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
754 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptEpilogueStub()
895 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
911 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
H A DMipsSERegisterInfo.cpp56 return &Mips::GPR32RegClass; in intRegClass()
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
H A DMipsSEInstrInfo.cpp90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
91 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
224 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
302 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
598 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
H A DMipsISelLowering.cpp4151 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
4155 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
4180 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
4799 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_W()
4808 Register LoadHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_W()
4809 Register LoadFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_W()
4810 Register Undef = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_W()
4854 Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D()
4855 Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D()
4873 Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D()
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H A DMips16InstrInfo.cpp76 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
H A DMipsSubtarget.cpp233 : &Mips::GPR32RegClass); in getCriticalPathRCs()
H A DMipsRegisterInfo.cpp54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
H A DMipsSEISelLowering.cpp67 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
3032 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitBPOSGE32()
3101 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitMSACBranchPseudo()
3333 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3518 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass in emitST_F16_PSEUDO()
3520 const bool UsingMips32 = RC == &Mips::GPR32RegClass; in emitST_F16_PSEUDO()
3521 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitST_F16_PSEUDO()
3570 : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass in emitLD_F16_PSEUDO()
3573 const bool UsingMips32 = RC == &Mips::GPR32RegClass; in emitLD_F16_PSEUDO()
3582 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass); in emitLD_F16_PSEUDO()
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H A DMipsAsmPrinter.cpp338 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; in printSavedRegsBitmask()
357 } else if (Mips::GPR32RegClass.contains(Reg)) in printSavedRegsBitmask()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandStore()
90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
91 Register Rb = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ()
118 Register R = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTTZ()
H A DARCInstrInfo.cpp285 assert(ARC::GPR32RegClass.contains(SrcReg) && in copyPhysReg()
287 assert(ARC::GPR32RegClass.contains(DestReg) && in copyPhysReg()
309 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
337 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
H A DARCRegisterInfo.cpp60 BaseReg = RS->FindUnusedReg(&ARC::GPR32RegClass); in replaceFrameIndex()
67 RS->scavengeRegisterBackwards(ARC::GPR32RegClass, II, false, SPAdj); in replaceFrameIndex()
208 assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand"); in eliminateFrameIndex()
H A DARCISelLowering.cpp100 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
531 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
575 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass); in LowerCallArguments()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
139 else if (RC == &BPF::GPR32RegClass) in storeRegToStackSlot()
160 else if (RC == &BPF::GPR32RegClass) in loadRegFromStackSlot()
H A DBPFISelLowering.cpp60 addRegisterClass(MVT::i32, &BPF::GPR32RegClass); in BPFTargetLowering()
266 return std::make_pair(0U, &BPF::GPR32RegClass); in getRegForInlineAsmConstraint()
365 SimpleTy == MVT::i64 ? &BPF::GPRRegClass : &BPF::GPR32RegClass); in LowerFormalArguments()
H A DBPFMISimplifyPatchable.cpp193 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp383 : &AArch64::GPR32RegClass; in materializeInt()
415 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
473 ResultReg = createResultReg(&AArch64::GPR32RegClass); in materializeGV()
1320 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()
1363 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()
1406 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()
1448 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()
1730 RC = &AArch64::GPR32RegClass; in emitLogicalOp_rs()
1836 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1841 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
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H A DAArch64CollectLOH.cpp500 for (MCPhysReg Reg : AArch64::GPR32RegClass) in handleNormalInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp78 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp221 return TryMatchDUP(&AArch64::GPR32RegClass, &AArch64::FPR32RegClass, in foldCopyDup()
H A DAArch64InstructionSelector.cpp576 : &AArch64::GPR32RegClass; in getRegClassForTypeOnBank()
620 : &AArch64::GPR32RegClass; in getMinClassForRegBank()
1608 TestReg, UseWReg ? AArch64::GPR32RegClass : AArch64::GPR64RegClass, in emitTestBit()
2321 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI); in earlySelect()
2685 DefSize == 32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in select()
2776 AArch64::GPR32RegClass, MRI); in select()
2811 AArch64::GPR32RegClass, MRI); in select()
2912 Register NewVal = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
3037 Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass); in select()
3181 } else if (DstRC == &AArch64::GPR32RegClass && in select()
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