Home
last modified time | relevance | path

Searched refs:GLD1_SXTW_MERGE_ZERO (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h400 GLD1_SXTW_MERGE_ZERO, enumerator
H A DAArch64ISelLowering.cpp2783 MAKE_CASE(AArch64ISD::GLD1_SXTW_MERGE_ZERO) in getTargetNodeName()
6149 AArch64ISD::GLD1_SXTW_MERGE_ZERO}, in getGatherVecOpcode()
6174 case AArch64ISD::GLD1_SXTW_MERGE_ZERO: in getSignExtendedGatherOpcode()
18971 case AArch64ISD::GLD1_SXTW_MERGE_ZERO: in performSVEAndCombine()
22329 const bool Extended = Opc == AArch64ISD::GLD1_SXTW_MERGE_ZERO || in performGLD1Combine()
24787 case AArch64ISD::GLD1_SXTW_MERGE_ZERO: in performSignExtendInRegCombine()
25382 case AArch64ISD::GLD1_SXTW_MERGE_ZERO: in PerformDAGCombine()
25500 return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_SXTW_MERGE_ZERO, in PerformDAGCombine()
H A DAArch64SVEInstrInfo.td72 def AArch64ld1_gather_sxtw_z : SDNode<"AArch64ISD::GLD1_SXTW_MERGE_ZERO", SDT_AArch64…