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Searched refs:GCC_GPU_GPLL0_DIV_CLK_SRC (Results 1 – 25 of 32) sorted by relevance

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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dqcom,gcc-sc7180.h47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 macro
H A Dqcom,gcc-qcm2290.h95 #define GCC_GPU_GPLL0_DIV_CLK_SRC 85 macro
H A Dqcom,sm7150-gcc.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 33 macro
H A Dqcom,gcc-sm6115.h82 #define GCC_GPU_GPLL0_DIV_CLK_SRC 74 macro
H A Dqcom,gcc-sc7280.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 macro
H A Dqcom,gcc-sm6125.h124 #define GCC_GPU_GPLL0_DIV_CLK_SRC 115 macro
H A Dqcom,gcc-sm8450.h56 #define GCC_GPU_GPLL0_DIV_CLK_SRC 44 macro
H A Dqcom,sm6375-gcc.h109 #define GCC_GPU_GPLL0_DIV_CLK_SRC 98 macro
H A Dqcom,sm8550-gcc.h42 #define GCC_GPU_GPLL0_DIV_CLK_SRC 31 macro
H A Dqcom,gcc-sdm845.h42 #define GCC_GPU_GPLL0_DIV_CLK_SRC 32 macro
H A Dqcom,gcc-sm8150.h48 #define GCC_GPU_GPLL0_DIV_CLK_SRC 38 macro
H A Dqcom,gcc-sm8250.h45 #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 macro
H A Dqcom,gcc-sm8350.h52 #define GCC_GPU_GPLL0_DIV_CLK_SRC 40 macro
H A Dqcom,sa8775p-gcc.h72 #define GCC_GPU_GPLL0_DIV_CLK_SRC 61 macro
H A Dqcom,gcc-sc8180x.h47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 macro
H A Dqcom,gcc-sc8280xp.h86 #define GCC_GPU_GPLL0_DIV_CLK_SRC 75 macro
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm4450.dtsi433 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
H A Dsm6375.dtsi1510 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
H A Dqcm2290.dtsi1547 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
H A Dsm6115.dtsi1793 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
H A Dsc8180x.dtsi2371 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
H A Dsm8350.dtsi2025 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
H A Dsc7180.dtsi2301 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
H A Dsm8150.dtsi2350 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
H A Dsdm845.dtsi3371 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

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