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Searched refs:GATE (Results 1 – 19 of 19) sorted by relevance

/freebsd/sys/dev/clk/rockchip/
H A Drk3399_cru.c58 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7),
59 GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6),
60 GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5),
61 GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4),
62 GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3),
63 GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2),
64 GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1),
65 GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0),
69 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7),
70 GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c", 1, 6),
[all …]
H A Drk3568_cru.c815 GATE(0, "sclk_core_src", "sclk_core_src_c", 0, 5),
818 GATE(0, "atclk_core", "atclk_core_div", 0, 8),
819 GATE(0, "gicclk_core", "gicclk_core_div", 0, 9),
820 GATE(0, "pclk_core_pre", "pclk_core_pre_div", 0, 10),
821 GATE(0, "periphclk_core_pre", "periphclk_core_pre_div", 0, 11),
837 GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 1, 9),
838 GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 1, 10),
839 GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 1, 11),
840 GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 1, 12),
847 GATE(CLK_GPU_SRC, "clk_gpu_src", "clk_gpu_pre_c", 2, 0),
[all …]
H A Drk3288_cru.c78 #define GATE(_idx, _clkname, _pname, _o, _s) \ macro
89 GATE(0, "sclk_acc_efuse", "xin24m", 0, 12),
90 GATE(0, "cpll_aclk_cpu", "cpll", 0, 11),
91 GATE(0, "gpll_aclk_cpu", "gpll", 0, 10),
92 GATE(0, "gpll_ddr", "gpll", 0, 9),
93 GATE(0, "dpll_ddr", "dpll", 0, 8),
94 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0, 7),
95 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_s", 0, 5),
96 GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_s", 0, 4),
97 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 3),
[all …]
H A Drk3328_cru.c253 GATE(0, "core_apll_clk", "apll", 0, 0),
254 GATE(0, "core_dpll_clk", "dpll", 0, 1),
255 GATE(0, "core_gpll_clk", "gpll", 0, 2),
262 GATE(SCLK_WIFI, "sclk_wifi", "sclk_wifi_c", 0, 10),
263 GATE(SCLK_RTC32K, "clk_rtc32k", "clk_rtc32k_c", 0, 11),
264 GATE(0, "core_npll_clk", "npll", 0, 12),
269 GATE(0, "clk_i2s0_div", "clk_i2s0_div_c", 1, 1),
270 GATE(0, "clk_i2s0_frac", "clk_i2s0_frac_f", 1, 2),
271 GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 1, 3),
272 GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 1, 4),
[all …]
H A Drk3568_pmucru.c163 GATE(XIN_OSC0_DIV, "xin_osc0_div", "xin_osc0_div_div", 0, 0),
164 GATE(CLK_RTC_32K, "clk_rtc_32k", "clk_rtc_32k_mux", 0, 1),
165 GATE(PCLK_PDPMU, "pclk_pdpmu", "pclk_pdpmu_pre", 0, 2),
166 GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 6),
167 GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 7),
170 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 1, 0),
171 GATE(CLK_I2C0, "clk_i2c0", "clk_i2c0_div", 1, 1),
172 GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 1, 2),
173 GATE(CLK_UART0_DIV, "sclk_uart0_div", "sclk_uart0_div_div", 1, 3),
174 GATE(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_frac_div", 1, 4),
[all …]
H A Drk3399_pmucru.c94 GATE(SCLK_SPI3_PMU, "clk_spi3_pmu", "clk_spi3_c", 0, 2),
95 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_sel", 0, 3),
96 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_sel", 0, 4),
97 GATE(SCLK_UART4_PMU, "clk_uart4_pmu", "clk_uart4_sel", 0, 5),
98 GATE(0, "clk_uart4_frac", "clk_uart4_frac_frac", 0, 6),
100 GATE(SCLK_WIFI_PMU, "clk_wifi_pmu", "clk_wifi_sel", 0, 8),
101 GATE(SCLK_I2C0_PMU, "clk_i2c0_src", "clk_i2c0_div", 0, 9),
102 GATE(SCLK_I2C4_PMU, "clk_i2c4_src", "clk_i2c4_div", 0, 10),
103 GATE(SCLK_I2C8_PMU, "clk_i2c8_src", "clk_i2c8_div", 0, 11),
107 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", 1, 0),
[all …]
H A Drk_cru.h50 #define GATE(_idx, _clkname, _pname, _o, _s) \ macro
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_per.c71 #define GATE(_id, cname, plist, _idx) \ macro
309 GATE(ISPB, "ispb", "clk_m", L(3)),
310 GATE(RTC, "rtc", "clk_s", L(4)),
311 GATE(TIMER, "timer", "clk_m", L(5)),
312 GATE(UARTA, "uarta", "pc_uarta" , L(6)),
313 GATE(UARTB, "uartb", "pc_uartb", L(7)),
314 GATE(GPIO, "gpio", "clk_m", L(8)),
315 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)),
316 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)),
317 GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)),
[all …]
H A Dtegra210_car.c122 #define GATE(_id, cname, plist, o, s) \ macro
247 GATE(TEGRA210_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
248 GATE(TEGRA210_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
249 GATE(0, "pllD_dsi_csi", "pllD_out0", PLLD_MISC, 21),
250 GATE(0, "pllP_hsio", "pllP_out0", PLLP_MISC1, 29),
251 GATE(0, "pllP_xusb", "pllP_hsio", PLLP_MISC1, 28),
H A Dtegra210_clk_pll.c208 #define GATE(_id, cname, plist, o, s) \ macro
510 GATE(0, "pllU_480", "pllU", PLLU_BASE, 22),
511 GATE(0, "pllU_60", "pllU_out2", PLLU_BASE, 23),
512 GATE(0, "pllU_48", "pllU_out1", PLLU_BASE, 25),
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c76 #define GATE(_id, cname, plist, _idx) \ macro
215 GATE(ISPB, "ispb", "clk_m", L(3)),
216 GATE(RTC, "rtc", "clk_s", L(4)),
217 GATE(TIMER, "timer", "clk_m", L(5)),
218 GATE(UARTA, "uarta", "pc_uarta" , L(6)),
219 GATE(UARTB, "uartb", "pc_uartb", L(7)),
220 GATE(VFIR, "vfir", "pc_vfir", L(7)),
222 GATE(SDMMC2, "sdmmc2", "pc_sdmmc2", L(9)),
223 GATE(SPDIF_OUT, "spdif_out", "pc_spdif_out", L(10)),
224 GATE(SPDIF_IN, "spdif_in", "pc_spdif_in", L(10)),
[all …]
H A Dtegra124_car.c121 #define GATE(_id, cname, plist, o, s) \ macro
256 GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
257 GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
/freebsd/sys/arm64/freescale/imx/
H A Dimx8mq_ccm.c168 GATE(IMX8MQ_ARM_PLL_OUT, "arm_pll_out", "arm_pll_bypass", 0x28, 21),
169 GATE(IMX8MQ_GPU_PLL_OUT, "gpu_pll_out", "gpu_pll_bypass", 0x18, 21),
170 GATE(IMX8MQ_VPU_PLL_OUT, "vpu_pll_out", "vpu_pll_bypass", 0x20, 21),
171 GATE(IMX8MQ_AUDIO_PLL1_OUT, "audio_pll1_out", "audio_pll1_bypass", 0x0, 21),
172 GATE(IMX8MQ_AUDIO_PLL2_OUT, "audio_pll2_out", "audio_pll2_bypass", 0x8, 21),
173 GATE(IMX8MQ_VIDEO_PLL1_OUT, "video_pll1_out", "video_pll1_bypass", 0x10, 21),
175 GATE(IMX8MQ_SYS1_PLL_40M_CG, "sys1_pll_40m_cg", "sys1_pll_out", 0x30, 9),
176 GATE(IMX8MQ_SYS1_PLL_80M_CG, "sys1_pll_80m_cg", "sys1_pll_out", 0x30, 11),
177 GATE(IMX8MQ_SYS1_PLL_100M_CG, "sys1_pll_100m_cg", "sys1_pll_out", 0x30, 13),
178 GATE(IMX8MQ_SYS1_PLL_133M_CG, "sys1_pll_133m_cg", "sys1_pll_out", 0x30, 15),
[all …]
H A Dimx8mp_ccm.c392 GATE(IMX8MP_AUDIO_PLL1_OUT, "audio_pll1_out", "audio_pll1_bypass", 0x00, 13),
393 GATE(IMX8MP_AUDIO_PLL2_OUT, "audio_pll2_out", "audio_pll2_bypass", 0x14, 13),
394 GATE(IMX8MP_VIDEO_PLL1_OUT, "video_pll1_out", "video_pll1_bypass", 0x28, 13),
395 GATE(IMX8MP_DRAM_PLL_OUT, "dram_pll_out", "dram_pll_bypass", 0x50, 13),
396 GATE(IMX8MP_GPU_PLL_OUT, "gpu_pll_out", "gpu_pll_bypass", 0x64, 11),
397 GATE(IMX8MP_VPU_PLL_OUT, "vpu_pll_out", "vpu_pll_bypass", 0x74, 11),
398 GATE(IMX8MP_ARM_PLL_OUT, "arm_pll_out", "arm_pll_bypass", 0x84, 11),
399 GATE(IMX8MP_SYS_PLL1_OUT, "sys_pll1_out", "sys_pll1_bypass", 0x94, 11),
400 GATE(IMX8MP_SYS_PLL2_OUT, "sys_pll2_out", "sys_pll2_bypass", 0x104, 11),
401 GATE(IMX8MP_SYS_PLL3_OUT, "sys_pll3_out", "sys_pll3_bypass", 0x114, 11),
[all …]
H A Dimx_ccm.h135 #define GATE(_id, _name, _pname, _o, _shift) \ macro
/freebsd/sys/riscv/sifive/
H A Dsifive_prci.c146 #define GATE(_id, _name, _parent_name, _base) \ macro
154 #define GATE_END GATE(0, NULL, NULL, 0)
241 GATE(FU740_PRCI_PCIEAUXCLK, "pcieauxclk", "hfclk", FU740_PRCI_PCIEAUX_GATE),
/freebsd/crypto/heimdal/lib/wind/
H A DUnicodeData.txt8129 2ED4;CJK RADICAL C-SIMPLIFIED GATE;So;0;ON;;;;;N;;;;;
8329 2FA8;KANGXI RADICAL GATE;So;0;ON;<compat> 9580;;;;N;;;;;
H A DNormalizationTest.txt1604 2FA8;2FA8;2FA8;9580;9580; # (⾨; ⾨; ⾨; 門; 門; ) KANGXI RADICAL GATE
/freebsd/share/misc/
H A Dusb_vendors6948 018b Hi-MD SOUND GATE