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Searched refs:FirstReg (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchAsmPrinter.cpp101 unsigned RegID = MO.getReg().id(), FirstReg; in PrintAsmOperand() local
103 FirstReg = LoongArch::XR0; in PrintAsmOperand()
105 FirstReg = LoongArch::VR0; in PrintAsmOperand()
107 FirstReg = LoongArch::F0_64; in PrintAsmOperand()
109 FirstReg = LoongArch::F0; in PrintAsmOperand()
114 RegID - FirstReg + in PrintAsmOperand()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp391 Register FirstReg; in CreateRegs() local
398 if (!FirstReg) FirstReg = R; in CreateRegs()
401 return FirstReg; in CreateRegs()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp494 Register FirstReg; in ScanInstruction() local
501 if (FirstReg) { in ScanInstruction()
503 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
506 FirstReg = Reg; in ScanInstruction()
510 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3384 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3389 return loadImmediate(ImmOp32, FirstReg, MCRegister(), true, false, IDLoc, Out, in expandLoadSingleImmToGPR()
3401 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3419 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3440 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr), in expandLoadSingleImmToFPR()
3453 MCRegister FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3460 if (loadImmediate(ImmOp64, FirstReg, MCRegister(), false, false, IDLoc, in expandLoadDoubleImmToGPR()
3464 if (loadImmediate(Hi_32(ImmOp64), FirstReg, MCRegister(), true, false, in expandLoadDoubleImmToGPR()
3468 if (loadImmediate(0, nextReg(FirstReg), MCRegister(), true, false, IDLoc, in expandLoadDoubleImmToGPR()
3500 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp2254 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord() argument
2310 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2312 if (FirstReg == SecondReg) in CanFormLdStDWord()
2413 Register FirstReg, SecondReg; in RescheduleOps() local
2421 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2428 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2434 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2448 .addReg(FirstReg) in RescheduleOps()
2466 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2467 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1695 if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1696 Reg = FirstReg; in printVectorList()
1697 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1698 Reg = FirstReg; in printVectorList()
1699 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1700 Reg = FirstReg; in printVectorList()
1701 else if (MCRegister FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) in printVectorList() local
1702 Reg = FirstReg; in printVectorList()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4541 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs() argument
4546 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4555 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
4578 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
4594 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg() argument
4604 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4618 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4667 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4741 unsigned FirstReg = 0; in HandleByVal() local
4757 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
[all …]
H A DMipsISelLowering.h610 const Argument *FuncArg, unsigned FirstReg,
619 unsigned FirstReg, unsigned LastReg,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1891 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
1892 Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() - in addVectorListOperands()
4547 unsigned FirstReg, ElementWidth; in tryParseMatrixTileList() local
4548 auto ParseRes = ParseMatrixTile(FirstReg, ElementWidth); in tryParseMatrixTileList()
4556 unsigned PrevReg = FirstReg; in tryParseMatrixTileList()
4559 AArch64Operand::ComputeRegsForAlias(FirstReg, DRegs, ElementWidth); in tryParseMatrixTileList()
4562 SeenRegs.insert(FirstReg); in tryParseMatrixTileList()
4637 MCRegister FirstReg; in tryParseVectorList() local
4638 auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch); in tryParseVectorList()
4648 MCRegister PrevReg = FirstReg; in tryParseVectorList()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp38 template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
338 template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
346 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg); in DecodeSimpleRegisterClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1627 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
1633 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
1634 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
1636 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
1638 Register OldFirstReg = FirstReg; in insertSelect()
1639 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
1640 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
1645 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
H A DPPCISelLowering.cpp7066 const MCRegister FirstReg = State.AllocateReg(PPC::R9); in CC_AIX() local
7068 assert(FirstReg && SecondReg && in CC_AIX()
7071 CCValAssign::getCustomReg(ValNo, ValVT, FirstReg, RegVT, LocInfo)); in CC_AIX()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp3251 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
3259 FirstReg = Count - 1; in computeCalleeSaveRegisterPairs()
3268 for (unsigned i = FirstReg; i < Count; i += RegInc) { in computeCalleeSaveRegisterPairs()
3305 bool IsFirst = i == FirstReg; in computeCalleeSaveRegisterPairs()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4926 MCRegister FirstReg = Reg; in parseVectorList() local
4934 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
5061 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
5065 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E, *this)); in parseVectorList()
5070 FirstReg, Count, LaneIndex, (Spacing == 2), S, E, *this)); in parseVectorList()