Home
last modified time | relevance | path

Searched refs:FirstReg (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp386 Register FirstReg; in CreateRegs() local
393 if (!FirstReg) FirstReg = R; in CreateRegs()
396 return FirstReg; in CreateRegs()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp491 unsigned FirstReg = 0; in ScanInstruction() local
497 if (FirstReg != 0) { in ScanInstruction()
499 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
502 FirstReg = Reg; in ScanInstruction()
506 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3435 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3440 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3452 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3470 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3493 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr), in expandLoadSingleImmToFPR()
3506 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3513 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, in expandLoadDoubleImmToGPR()
3517 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3521 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
3555 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1682 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList()
1683 Reg = FirstReg; in printVectorList()
1684 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList()
1685 Reg = FirstReg; in printVectorList()
1686 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList()
1687 Reg = FirstReg; in printVectorList()
1688 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) in printVectorList()
1689 Reg = FirstReg; in printVectorList()
1669 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) printVectorList() local
1671 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) printVectorList() local
1673 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) printVectorList() local
1675 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) printVectorList() local
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp2257 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord() argument
2313 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2315 if (FirstReg == SecondReg) in CanFormLdStDWord()
2416 Register FirstReg, SecondReg; in RescheduleOps() local
2424 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2431 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2437 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2451 .addReg(FirstReg) in RescheduleOps()
2469 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2470 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4368 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs() argument
4373 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4382 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
4405 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
4421 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg() argument
4431 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4445 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4494 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4568 unsigned FirstReg = 0; in HandleByVal() local
4584 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
[all …]
H A DMipsISelLowering.h577 const Argument *FuncArg, unsigned FirstReg,
586 unsigned FirstReg, unsigned LastReg,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1862 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
1863 Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() - in addVectorListOperands()
4416 unsigned FirstReg, ElementWidth; in tryParseMatrixTileList() local
4417 auto ParseRes = ParseMatrixTile(FirstReg, ElementWidth); in tryParseMatrixTileList()
4425 unsigned PrevReg = FirstReg; in tryParseMatrixTileList()
4428 AArch64Operand::ComputeRegsForAlias(FirstReg, DRegs, ElementWidth); in tryParseMatrixTileList()
4431 SeenRegs.insert(FirstReg); in tryParseMatrixTileList()
4506 MCRegister FirstReg; in tryParseVectorList() local
4507 auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch); in tryParseVectorList()
4517 int64_t PrevReg = FirstReg; in tryParseVectorList()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp41 template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
330 template <unsigned RegClassID, unsigned FirstReg, unsigned NumRegsInClass>
338 AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg); in DecodeSimpleRegisterClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1629 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
1635 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
1636 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
1638 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
1640 Register OldFirstReg = FirstReg; in insertSelect()
1641 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
1642 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
1647 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
H A DPPCISelLowering.cpp7054 const unsigned FirstReg = State.AllocateReg(PPC::R9); in CC_AIX() local
7056 assert(FirstReg && SecondReg && in CC_AIX()
7059 CCValAssign::getCustomReg(ValNo, ValVT, FirstReg, RegVT, LocInfo)); in CC_AIX()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp2958 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
2966 FirstReg = Count - 1; in computeCalleeSaveRegisterPairs()
2973 for (unsigned i = FirstReg; i < Count; i += RegInc) { in computeCalleeSaveRegisterPairs()
3002 bool IsFirst = i == FirstReg; in computeCalleeSaveRegisterPairs()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4897 unsigned FirstReg = Reg; in parseVectorList() local
4905 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
5032 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
5036 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E, *this)); in parseVectorList()
5041 FirstReg, Count, LaneIndex, (Spacing == 2), S, E, *this)); in parseVectorList()