3435   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadSingleImmToGPR()  local
3440   return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc,  in expandLoadSingleImmToGPR()
3452   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadSingleImmToFPR()  local
3470     TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);  in expandLoadSingleImmToFPR()
3493   TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr),  in expandLoadSingleImmToFPR()
3506   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadDoubleImmToGPR()  local
3513       if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false,  in expandLoadDoubleImmToGPR()
3517       if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false,  in expandLoadDoubleImmToGPR()
3521       if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false,  in expandLoadDoubleImmToGPR()
3555     TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI);  in expandLoadDoubleImmToGPR()
3557     TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);  in expandLoadDoubleImmToGPR()
3558     TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);  in expandLoadDoubleImmToGPR()
3571   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadDoubleImmToFPR()  local
3590       TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3600       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3601       TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3603       TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3604       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3630   TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg,  in expandLoadDoubleImmToFPR()
4412   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandTrunc()  local
4429                 FirstReg, SecondReg, IDLoc, STI);  in expandTrunc()
4437               FirstReg, SecondReg, IDLoc, STI);  in expandTrunc()
5354   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadStoreDMacro()  local
5355   unsigned SecondReg = nextReg(FirstReg);  in expandLoadStoreDMacro()
5360   warnIfRegIndexIsAT(FirstReg, IDLoc);  in expandLoadStoreDMacro()
5374   if (FirstReg != BaseReg || !IsLoad) {  in expandLoadStoreDMacro()
5375     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandLoadStoreDMacro()
5379     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandLoadStoreDMacro()
5401   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandStoreDM1Macro()  local
5402   unsigned SecondReg = nextReg(FirstReg);  in expandStoreDM1Macro()
5407   warnIfRegIndexIsAT(FirstReg, IDLoc);  in expandStoreDM1Macro()
5420     std::swap(FirstReg, SecondReg);  in expandStoreDM1Macro()
5422   TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandStoreDM1Macro()