| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 105 DAG_FUNCTION(trunc, 1, 0, experimental_constrained_trunc, FTRUNC)
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| H A D | VPIntrinsics.def | 458 VP_PROPERTY_FUNCTIONAL_SDOPC(FTRUNC)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 988 FTRUNC, enumerator
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| H A D | BasicTTIImpl.h | 2046 ISD = ISD::FTRUNC; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 395 ISD::FROUNDEVEN, ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM}, in AMDGPUTargetLowering()
535 ISD::FFLOOR, ISD::FTRUNC, ISD::FMUL, in AMDGPUTargetLowering()
660 case ISD::FTRUNC: in fnegFoldsIntoOpcode()
1383 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG); in LowerOperation()
1961 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq); in LowerDIVREM24()
2080 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2); in LowerUDIVREM64()
2358 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags); in LowerFREM()
2372 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
2503 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND()
2533 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
[all …]
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| H A D | R600ISelLowering.cpp | 104 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR}, in R600TargetLowering()
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| H A D | AMDGPUISelDAGToDAG.cpp | 160 case ISD::FTRUNC: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 229 case ISD::FTRUNC: return "ftrunc"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 149 case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break; in SoftenFloatResult()
1473 case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break; in ExpandFloatResult()
2620 case ISD::FTRUNC: in PromoteFloatResult()
3062 case ISD::FTRUNC: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 421 case ISD::FTRUNC: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 122 case ISD::FTRUNC: in ScalarizeVectorResult()
1209 case ISD::FTRUNC: in SplitVectorResult()
3203 case ISD::FTRUNC: in SplitVectorOperand()
4552 case ISD::FTRUNC: in WidenVectorResult()
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| H A D | DAGCombiner.cpp | 1947 case ISD::FTRUNC: return visitFTRUNC(N); in visit()
17485 TLI.isOperationLegalOrCustom(ISD::FTRUNC, VT) && in visitFREM()
17490 SDValue Rnd = DAG.getNode(ISD::FTRUNC, DL, VT, Div); in visitFREM()
17699 if (!TLI.isOperationLegal(ISD::FTRUNC, VT) || in foldFPToIntToFP()
17708 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0)); in foldFPToIntToFP()
17712 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0)); in foldFPToIntToFP()
18036 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0); in visitFTRUNC()
18044 case ISD::FTRUNC: in visitFTRUNC()
18840 TLI.isOperationLegal(ISD::FTRUNC, STMemType)) { in getTruncatedStoreValue()
18841 Val = DAG.getNode(ISD::FTRUNC, SDLoc(ST), STMemType, Val); in getTruncatedStoreValue()
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| H A D | LegalizeDAG.cpp | 4604 case ISD::FTRUNC: in ConvertNodeToLibcall()
5538 case ISD::FTRUNC: in PromoteNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 455 case ISD::FTRUNC: in NVPTXTargetLowering()
770 ISD::FROUNDEVEN, ISD::FTRUNC}) { in NVPTXTargetLowering()
2584 SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA); in LowerFROUND32()
2596 SDValue RoundedAForSmallA = DAG.getNode(ISD::FTRUNC, SL, VT, A); in LowerFROUND32()
2616 SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA); in LowerFROUND64()
2628 DAG.getNode(ISD::FTRUNC, SL, VT, A); in LowerFROUND64()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 829 ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 324 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); in PPCTargetLowering()
462 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in PPCTargetLowering()
467 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in PPCTargetLowering()
866 setOperationAction(ISD::FTRUNC, VT, Expand); in PPCTargetLowering()
930 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
1028 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
1234 setOperationAction(ISD::FTRUNC, MVT::f128, Legal); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 551 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); in AArch64TargetLowering()
772 ISD::FTRUNC, in AArch64TargetLowering()
816 setOperationPromotedToType(ISD::FTRUNC, V4Narrow, MVT::v4f32); in AArch64TargetLowering()
847 setOperationAction(ISD::FTRUNC, V8Narrow, Legal); in AArch64TargetLowering()
865 ISD::FRINT, ISD::FTRUNC, ISD::FROUND, in AArch64TargetLowering()
1194 ISD::FROUNDEVEN, ISD::FTRUNC, ISD::FMINNUM, in AArch64TargetLowering()
1349 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1608 setOperationAction(ISD::FTRUNC, VT, Custom); in AArch64TargetLowering()
2075 setOperationAction(ISD::FTRUNC, VT, Default); in addTypeForFixedLengthSVE()
6835 case ISD::FTRUNC: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1212 case ISD::FTRUNC: in PreprocessISelDAG()
1230 case ISD::FTRUNC: Imm = 0xB; break; in PreprocessISelDAG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 136 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 522 setOperationAction(ISD::FTRUNC, VT, Legal); in SystemZTargetLowering()
582 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in SystemZTargetLowering()
623 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in SystemZTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 447 ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FRINT, ISD::FROUND, in RISCVTargetLowering()
461 ISD::FTRUNC, ISD::FRINT, ISD::FROUND, in RISCVTargetLowering()
985 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND, in RISCVTargetLowering()
1374 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND, in RISCVTargetLowering()
3012 case ISD::FTRUNC: in matchRoundingOp()
3035 // Expand vector FTRUNC, FCEIL, FFLOOR, FROUND, VP_FCEIL, VP_FFLOOR, VP_FROUND
3115 case ISD::FTRUNC: in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
6764 case ISD::FTRUNC: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 540 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 892 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); in ARMTargetLowering()
914 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand); in ARMTargetLowering()
932 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand); in ARMTargetLowering()
1074 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); in ARMTargetLowering()
1514 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in ARMTargetLowering()
1530 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1507 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG, in HexagonTargetLowering()
1656 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 154 setOperationAction(ISD::FTRUNC, MVT::f16, Promote); in MipsSETargetLowering()
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