| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInsertReadWriteCSR.cpp | 86 MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) { in INITIALIZE_PASS()
96 assert(!MI.modifiesRegister(RISCV::FRM, /*TRI=*/nullptr) && in INITIALIZE_PASS()
107 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in INITIALIZE_PASS()
164 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in emitWriteRoundingMode()
|
| H A D | RISCVInstrInfoZvfbf.td | 24 let Uses = [FRM, VL, VTYPE] in
30 RVVConstraint = WidenV, Uses = [FRM, VL, VTYPE], mayRaiseFPException = true,
|
| H A D | RISCVInstrInfoV.td | 1378 let Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {
1386 Uses = [FRM, VL, VTYPE],
1401 } // Constraints = "@earlyclobber $vd", Uses = [FRM, VL, VTYPE], mayRaiseFPException = true, DestEE…
1404 let Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {
1412 Uses = [FRM, VL, VTYPE], mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
1414 } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM, VL, VTYPE], mayRaiseFP…
1417 let Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {
1429 let Uses = [FRM, VL, VTYPE], mayRaiseFPException = true, DestEEW = EEWSEWx2 in {
1434 } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV, Uses = [FRM, VL, VTYPE], mayRaiseFP…
1437 let Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {
[all …]
|
| H A D | RISCVInstrInfoXSfmm.td | 249 let Uses = [FRM], mayRaiseFPException = true in
264 let Uses = [FRM], mayRaiseFPException = true in {
|
| H A D | RISCVInstrInfoXAndes.td | 665 let Uses = [FRM, VL, VTYPE] in
683 Uses = [FRM, VL, VTYPE], mayRaiseFPException = true in {
|
| H A D | RISCVInstrInfo.td | 2041 def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
2043 def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
2044 def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
2045 def SwapFRMImm : SwapSysRegImm<SysRegFRM, [FRM]>;
2056 def ReadFCSR : ReadSysReg<SysRegFCSR, [FRM, FFLAGS]>;
2057 def WriteFCSR : WriteSysReg<SysRegFCSR, [FRM, FFLAGS]>;
2058 def WriteFCSRImm : WriteSysRegImm<SysRegFCSR, [FRM, FFLAGS]>;
|
| H A D | RISCVInstrInfo.cpp | 2011 const MachineOperand &FRM = Root.getOperand(FrmOpIdx); in finalizeInsInstrs() local
2020 MIB.add(FRM); in finalizeInsInstrs()
2021 if (FRM.getImm() == RISCVFPRndMode::DYN) in finalizeInsInstrs()
2022 MIB.addUse(RISCV::FRM, RegState::Implicit); in finalizeInsInstrs()
3037 !MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) { in verifyInstruction()
|
| H A D | RISCVRegisterInfo.cpp | 165 markSuperRegs(Reserved, RISCV::FRM); in getReservedRegs()
|
| H A D | RISCVISelLowering.cpp | 3322 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Op.getOpcode()); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local
3323 assert(FRM != RISCVFPRndMode::Invalid); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3325 DAG.getTargetConstant(FRM, DL, XLenVT), VL); in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
3421 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Op.getOpcode()); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() local
3422 assert(FRM != RISCVFPRndMode::Invalid); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
3425 {Chain, Src, Mask, DAG.getTargetConstant(FRM, DL, XLenVT), VL}); in lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
3481 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Op.getOpcode()); in lowerFTRUNC_FCEIL_FFLOOR_FROUND() local
3483 DAG.getTargetConstant(FRM, DL, Subtarget.getXLenVT())); in lowerFTRUNC_FCEIL_FFLOOR_FROUND()
17643 RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Src.getOpcode()); in performFP_TO_INTCombine() local
17645 if (FRM == RISCVFPRndMode::Invalid) in performFP_TO_INTCombine()
[all …]
|
| H A D | RISCVInstrInfoXSf.td | 240 Uses = [FRM, VL, VTYPE] in {
|
| H A D | RISCVRegisterInfo.td | 848 def FRM : RISCVReg<0, "frm">;
|
| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | ste-href-family-pinctrl.dtsi | 19 pins = "GPIO216_AG12"; /* FRM */
57 "GPIO216_AG12", /* FRM */
|
| H A D | ste-snowball.dts | 565 pins = "GPIO144_B13"; /* FRM */
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 347 FRM, enumerator
381 RISCVFPRndMode::RoundingMode FRM; member
409 FRMOp FRM; member
442 case KindTy::FRM: in RISCVOperand()
443 FRM = o.FRM; in RISCVOperand()
646 bool isFRMArg() const { return Kind == KindTy::FRM; } in isFRMArg()
647 bool isFRMArgLegacy() const { return Kind == KindTy::FRM; } in isFRMArgLegacy()
648 bool isRTZArg() const { return isFRMArg() && FRM.FRM == RISCVFPRndMode::RTZ; } in isRTZArg()
1014 assert(Kind == KindTy::FRM && "Invalid type access!"); in getFRM()
1015 return FRM.FRM; in getFRM()
[all …]
|