| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 96 DAG_FUNCTION(powi, 2, 1, experimental_constrained_powi, FPOWI)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1016 FPOWI, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 130 case ISD::FPOWI: in SoftenFloatResult()
714 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI; in SoftenFloatRes_ExpOp()
1607 case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi); break; in ExpandFloatResult()
2882 case ISD::FPOWI: in PromoteFloatResult()
3366 case ISD::FPOWI: in SoftPromoteHalfResult()
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| H A D | SelectionDAGDumper.cpp | 331 case ISD::FPOWI: return "fpowi"; in getOperationName()
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| H A D | LegalizeVectorOps.cpp | 426 case ISD::FPOWI: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 63 case ISD::FPOWI: in ScalarizeVectorResult()
1135 case ISD::FPOWI: in SplitVectorResult()
4853 case ISD::FPOWI: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4860 case ISD::FPOWI: in ConvertNodeToLibcall()
5729 case ISD::FPOWI: { in PromoteNode()
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| H A D | LegalizeIntegerTypes.cpp | 2047 case ISD::FPOWI: in PromoteIntegerOperand()
2654 N->getOpcode() == ISD::FPOWI || N->getOpcode() == ISD::STRICT_FPOWI; in PromoteIntOp_ExpOp()
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| H A D | SelectionDAGBuilder.cpp | 5973 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); in ExpandPowI()
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| H A D | SelectionDAG.cpp | 5791 case ISD::FPOWI: in isKnownNeverNaN()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 859 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 148 case ISD::FPOWI: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 219 ISD::FSIN, ISD::FCOS, ISD::FPOW, ISD::FPOWI, in SITargetLowering()
490 setOperationAction({ISD::FPOW, ISD::FPOWI}, MVT::f16, Promote); in SITargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 182 setOperationAction(ISD::FPOWI, MVT::f16, Promote); in MipsSETargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 536 setOperationAction({ISD::FREM, ISD::FPOW, ISD::FPOWI, in RISCVTargetLowering()
552 setOperationAction(ISD::FPOWI, MVT::i32, Custom); in RISCVTargetLowering()
7440 case ISD::FPOWI: { in LowerOperation()
7448 DAG.getNode(ISD::FPOWI, DL, MVT::f32, Op0, Op.getOperand(1)); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 749 for (auto Op : {ISD::FREM, ISD::FPOW, ISD::FPOWI, in AArch64TargetLowering()
1719 setOperationAction(ISD::FPOWI, VT, Expand); in AArch64TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1210 setOperationAction(ISD::FPOWI, MVT::f128, Expand); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1505 setOperationAction(ISD::FPOWI, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 622 setOperationAction(ISD::FPOWI, VT, Action); in X86TargetLowering()
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