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Searched refs:FP32 (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td22 def LTER : UnaryRR <"lter", 0x32, null_frag, FP32, FP32>;
32 def LEDR : UnaryRR <"ledr", 0x35, null_frag, FP32, FP64>;
33 def LEXR : UnaryRRE<"lexr", 0xB366, null_frag, FP32, FP128>;
36 def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>;
41 def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64, FP32>;
42 def LXER : UnaryRRE<"lxer", 0xB326, null_frag, FP128, FP32>;
50 def CEFR : UnaryRRE<"cefr", 0xB3B4, null_frag, FP32, GR32>;
54 def CEGR : UnaryRRE<"cegr", 0xB3C4, null_frag, FP32, GR64>;
61 def CFER : BinaryRRFe<"cfer", 0xB3B8, GR32, FP32>;
65 def CGER : BinaryRRFe<"cger", 0xB3C8, GR64, FP32>;
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H A DSystemZInstrFP.td21 def SelectF32 : SelectWrapper<f32, FP32>;
28 defm CondStoreF32 : CondStores<FP32, simple_store,
41 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>;
48 def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
55 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
65 def LTEBR : UnaryRRE<"ltebr", 0xB302, null_frag, FP32, FP32>;
74 def LTEBRCompare_Pseudo : Pseudo<(outs), (ins FP32:$R1), []>;
78 defm : CompareZeroFP<LTEBRCompare_Pseudo, FP32>;
90 def CPSDRhs : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP16, FP16, FP32>;
103 // fcopysign with an FP32 result.
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H A DSystemZInstrDFP.td35 def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
41 def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
235 def TDCET : TestRXE<"tdcet", 0xED50, null_frag, FP32>;
242 def TDGET : TestRXE<"tdget", 0xED51, null_frag, FP32>;
H A DSystemZRegisterInfo.td261 defm FP32 : SystemZRegClass<"FP32", [f32], 32, (sequence "F%uS", 0, 15)>;
H A DSystemZInstrVector.td2228 defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_h32>;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.td30 def FP32 : WebAssemblyReg<"%FP32">;
63 def I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>;
H A DWebAssemblyRegisterInfo.cpp45 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32, in getReservedRegs()
146 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}}; in getFrameRegister()
H A DWebAssemblyFrameLowering.cpp188 : WebAssembly::FP32; in getFPReg()
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DMips.h60 enum FPModeEnum { FPXX, FP32, FP64 } FPMode; enumerator
93 return FP32; in getDefaultFPMode()
357 FPMode = FP32; in handleTargetFeatures()
H A DMips.cpp148 case FP32: in getTargetDefines()
307 if (FPMode == FP32 && HasMSA) { in validateTarget()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector.td1316 // Zvfbfmin - Vector convert BF16 to FP32
1387 // Zvfbfmin - Vector convert FP32 to BF16
1454 // Zvfbfmin - Vector convert FP32 to BF16
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Features.td167 "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;
562 "Enable Armv9.6-A FP16 to FP32 Matrix Multiply instructions", [FeatureSVE]>;
H A DAArch64InstrFormats.td6574 // FCVTN, FCVTN2 (FP32 to FP8)
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td1301 "SiFive FP32-to-int8 Ranged Clip Instructions",
1306 "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td2836 // SVE ACLE: 7.4/5. FP64/FP32 matrix multiply extensions
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOP3PInstructions.td914 // FP32 denorm mode is respected, rounding mode is not. Exceptions are not supported.