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Searched refs:FNMSUB (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedPredicates.td59 FNMSUB,
H A DPPCISelLowering.h171 FNMSUB, enumerator
H A DP10InstrResources.td210 FNMSUB,
H A DP9InstrResources.td428 FNMSUB,
H A DPPCISelLowering.cpp1816 case PPCISD::FNMSUB: return "PPCISD::FNMSUB"; in getTargetNodeName()
11423 return DAG.getNode(PPCISD::FNMSUB, dl, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
16708 case PPCISD::FNMSUB: in PerformDAGCombine()
18542 return PPCISD::FNMSUB; in invertFMAOpcode()
18543 case PPCISD::FNMSUB: in invertFMAOpcode()
18560 case PPCISD::FNMSUB: in getNegatedExpression()
H A DPPCInstrInfo.td265 def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>;
3036 defm FNMSUB : AForm_1r<63, 30,
3441 (FNMSUB $A, $B, $C)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp380 CASE_FMA4_PACKED_RR(FNMSUB) in printFMAComments()
381 CASE_FMA4_SCALAR_RR(FNMSUB) in printFMAComments()
384 CASE_FMA4_PACKED_RM(FNMSUB) in printFMAComments()
385 CASE_FMA4_SCALAR_RM(FNMSUB) in printFMAComments()
391 CASE_FMA4_PACKED_MR(FNMSUB) in printFMAComments()
392 CASE_FMA4_SCALAR_MR(FNMSUB) in printFMAComments()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp2468 : RISCVMachineCombinerPattern::FNMSUB); in getFPFusedMultiplyPatterns()
2579 case RISCVMachineCombinerPattern::FNMSUB: in getCombinerObjective()
2630 case RISCVMachineCombinerPattern::FNMSUB: in getAddendOperandIdx()
2757 case RISCVMachineCombinerPattern::FNMSUB: { in genAlternativeCodeSequence()
3792 case CASE_VFMA_SPLATS(FNMSUB): in findCommutedOpIndices()
3823 case CASE_VFMA_OPCODE_VV(FNMSUB): in findCommutedOpIndices()
3977 case CASE_VFMA_SPLATS(FNMSUB): in commuteInstructionImpl()
4002 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSAC, FNMSUB) in commuteInstructionImpl()
4003 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSUB, FNMSAC) in commuteInstructionImpl()
4007 CASE_VFMA_CHANGE_OPCODE_VV(FNMSAC, FNMSUB) in commuteInstructionImpl()
[all …]
H A DRISCVInstrInfo.h57 FNMSUB, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h578 FNMSUB, enumerator
H A DX86InstrFragmentsSIMD.td576 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
H A DX86ISelLowering.cpp35179 NODE_NAME_CASE(FNMSUB) in getTargetNodeName()
54602 case X86ISD::FMSUB: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
54608 case X86ISD::FNMSUB: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
54625 case X86ISD::FNMADD: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
54628 case X86ISD::FNMSUB: Opcode = X86ISD::FNMADD; break; in negateFMAOpcode()
54644 case ISD::FMA: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
54650 case X86ISD::FNMSUB: Opcode = ISD::FMA; break; in negateFMAOpcode()
54683 SDValue NewNode = DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0), in combineFneg()
54716 case X86ISD::FNMSUB: in getNegatedExpression()
60646 case X86ISD::FNMSUB: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX2T99.td1184 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
H A DAArch64SchedThunderX3T110.td1292 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
H A DAArch64SchedNeoverseN3.td838 def : InstRW<[N3Write_4c_1V], (instregex "^(FMADD|FMSUB|FNMADD|FNMSUB)[DHS]rrr$")>;
H A DAArch64InstrInfo.td5532 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",