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Searched refs:FNEG (Results 1 – 25 of 48) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp538 ISD::FNEG, ISD::VSELECT, ISD::SELECT_CC, in AMDGPUTargetLowering()
620 ISD::FSUB, ISD::FNEG, in AMDGPUTargetLowering()
1579 if (Val.getOpcode() == ISD::FNEG) in peekFNeg()
1586 if (Val.getOpcode() == ISD::FNEG) in peekFPSignOps()
1694 return DAG.getNode(ISD::FNEG, DL, VT, Combined); in combineFMinMaxLegacy()
1964 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
2359 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2738 SDValue NegR = DAG.getNode(ISD::FNEG, DL, VT, R, Flags); in LowerFLOGCommon()
3047 SDValue NegPH = DAG.getNode(ISD::FNEG, SL, VT, PH, Flags); in lowerFEXP()
4552 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
[all …]
H A DAMDGPUISelDAGToDAG.cpp2859 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3ModsImpl()
2918 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
2988 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
3000 if (Lo.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
3005 if (Hi.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
3188 if (ModOpcode == ISD::FNEG) { in selectWMMAModsNegAbs()
3240 if (Element.getOpcode() != ISD::FNEG) in SelectWMMAModsF16Neg()
3260 if (ElV2f16.getOpcode() != ISD::FNEG) in SelectWMMAModsF16Neg()
3289 ModOpcode = (ElF16.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS; in SelectWMMAModsF16NegAbs()
3310 ModOpcode = (ElV2f16.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS; in SelectWMMAModsF16NegAbs()
[all …]
H A DSIISelLowering.cpp229 setOperationAction(ISD::FNEG, MVT::bf16, Legal); in SITargetLowering()
747 setOperationAction(ISD::FNEG, MVT::v2f16, Legal); in SITargetLowering()
812 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG}, in SITargetLowering()
820 setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v4f16, Custom); in SITargetLowering()
831 setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v2f16, Custom); in SITargetLowering()
5828 case ISD::FNEG: in LowerOperation()
6437 case ISD::FNEG: { in ReplaceNodeResults()
10481 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in lowerFastUnsafeFDIV()
10510 SDValue NegY = DAG.getNode(ISD::FNEG, SL, VT, Y); in lowerFastUnsafeFDIV64()
10660 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, in LowerFDIV32()
[all …]
H A DR600Instructions.td688 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
691 "FNEG $dst, $src0",
1208 def FNEG_R600 : FNEG<R600_Reg32>;
H A DAMDGPUTargetTransformInfo.cpp673 case ISD::FNEG: in getArithmeticInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def111 ADD_UNARY_VVP_OP(VVP_FNEG, FNEG) HANDLE_VP_TO_VVP(VP_FNEG, VVP_FNEG) REGISTER_PACKED(VVP_FNEG)
H A DVVPInstrPatternsVec.td134 /// FNEG {
179 /// } FNEG
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h958 FNEG, enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1939 case ISD::FNEG: return visitFNEG(N); in visit()
11314 return DAG.getNode(ISD::FNEG, DL, VT, Combined); in combineMinNumMaxNum()
15328 FPOpcode = ISD::FNEG; in foldBitcastedFPLogic()
15364 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp); in foldBitcastedFPLogic()
15469 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
15482 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
15501 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
16153 matcher.getNode(ISD::FNEG, SL, VT, Z)); in visitFSUBForFMACombine()
16164 matcher.getNode(ISD::FNEG, SL, VT, YZ.getOperand(0)), in visitFSUBForFMACombine()
16190 if (matcher.match(N0, ISD::FNEG) && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
[all …]
H A DLegalizeFloatTypes.cpp114 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; in SoftenFloatResult()
1444 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
1544 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1754 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1755 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
2613 case ISD::FNEG: in PromoteFloatResult()
3054 case ISD::FNEG: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp392 case ISD::FNEG: in LegalizeOp()
911 case ISD::FNEG: in Expand()
1686 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandFSUB()
H A DSelectionDAGBuilder.h544 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); } in visitFNeg()
H A DLegalizeDAG.cpp1648 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) { in ExpandFCOPYSIGN()
1650 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue); in ExpandFCOPYSIGN()
3599 case ISD::FNEG: in ExpandNode()
3753 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) { in ExpandNode()
3755 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); in ExpandNode()
4368 SDValue Neg = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(2), Flags); in ExpandNode()
5539 case ISD::FNEG: in PromoteNode()
H A DSelectionDAGDumper.cpp206 case ISD::FNEG: return "fneg"; in getOperationName()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp952 { ISD::FNEG, MVT::v8f64, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
967 { ISD::FNEG, MVT::v16f32, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1154 { ISD::FNEG, MVT::v4f64, { 1, 1, 1, 2 } }, // vxorpd in getArithmeticInstrCost()
1155 { ISD::FNEG, MVT::v8f32, { 1, 1, 1, 2 } }, // vxorps in getArithmeticInstrCost()
1256 { ISD::FNEG, MVT::v4f64, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/ in getArithmeticInstrCost()
1257 { ISD::FNEG, MVT::v8f32, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/ in getArithmeticInstrCost()
1402 { ISD::FNEG, MVT::f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1403 { ISD::FNEG, MVT::f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1404 { ISD::FNEG, MVT::v4f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1405 { ISD::FNEG, MVT::v2f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1796 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1903 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1906 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1925 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
2922 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
3066 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3283 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
612 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>;
1117 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>;
H A DAArch64SchedCyclone.td436 // FABS,FNEG are WriteF
H A DAArch64SchedExynosM3.td545 def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td161 defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
H A DMipsInstrFPU.td537 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td190 (instregex "FNEG(D|S)$"),
1057 (instregex "FNEG(D|S)_rec$"),
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td120 defm FNEG : FT_XZ<0b000111, "fneg", UnOpFrag<(fneg node:$Src)>>;
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def367 VP_PROPERTY_FUNCTIONAL_SDOPC(FNEG)
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1752 case ISD::FNEG: in getArithmeticInstrCost()

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