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Searched refs:FNEG (Results 1 – 25 of 49) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp551 ISD::FNEG, ISD::VSELECT, ISD::SELECT_CC, in AMDGPUTargetLowering()
633 ISD::FSUB, ISD::FNEG, in AMDGPUTargetLowering()
1636 if (Val.getOpcode() == ISD::FNEG) in peekFNeg()
1643 if (Val.getOpcode() == ISD::FNEG) in peekFPSignOps()
1751 return DAG.getNode(ISD::FNEG, DL, VT, Combined); in combineFMinMaxLegacy()
2021 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq); in LowerDIVREM24()
2416 SDValue Neg = DAG.getNode(ISD::FNEG, SL, VT, Trunc, Flags); in LowerFREM()
2795 SDValue NegR = DAG.getNode(ISD::FNEG, DL, VT, R, Flags); in LowerFLOGCommon()
3105 SDValue NegPH = DAG.getNode(ISD::FNEG, SL, VT, PH, Flags); in lowerFEXP()
4780 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
[all …]
H A DAMDGPUISelDAGToDAG.cpp3021 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3ModsImpl()
3080 if (In.getOpcode() == ISD::FABS || In.getOpcode() == ISD::FNEG) in SelectVOP3NoMods()
3150 if (Src.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
3162 if (Lo.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
3167 if (Hi.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
3248 if (ShuffleSrc.getOpcode() == ISD::FNEG) { in SelectVOP3PMods()
3377 if (ModOpcode == ISD::FNEG) { in selectWMMAModsNegAbs()
3429 if (Element.getOpcode() != ISD::FNEG) in SelectWMMAModsF16Neg()
3449 if (ElV2f16.getOpcode() != ISD::FNEG) in SelectWMMAModsF16Neg()
3478 ModOpcode = (ElF16.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS; in SelectWMMAModsF16NegAbs()
[all …]
H A DSIISelLowering.cpp236 setOperationAction(ISD::FNEG, MVT::bf16, Legal); in SITargetLowering()
763 setOperationAction(ISD::FNEG, {MVT::v2f16, MVT::v2bf16}, Legal); in SITargetLowering()
840 setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG}, in SITargetLowering()
848 setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v4f16, Custom); in SITargetLowering()
859 setOperationAction({ISD::FNEG, ISD::FABS}, MVT::v2f16, Custom); in SITargetLowering()
6169 case ISD::FNEG: in LowerOperation()
6806 case ISD::FNEG: { in ReplaceNodeResults()
11138 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS); in lowerFastUnsafeFDIV()
11167 SDValue NegY = DAG.getNode(ISD::FNEG, SL, VT, Y); in lowerFastUnsafeFDIV64()
11254 SDValue NegRHSExt = DAG.getNode(ISD::FNEG, SL, MVT::f32, RHSExt); in LowerFDIV16()
[all …]
H A DR600Instructions.td688 class FNEG <RegisterClass rc> : AMDGPUShaderInst <
691 "FNEG $dst, $src0",
1208 def FNEG_R600 : FNEG<R600_Reg32>;
H A DAMDGPUTargetTransformInfo.cpp675 case ISD::FNEG: in getArithmeticInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def111 ADD_UNARY_VVP_OP(VVP_FNEG, FNEG) HANDLE_VP_TO_VVP(VP_FNEG, VVP_FNEG) REGISTER_PACKED(VVP_FNEG)
H A DVVPInstrPatternsVec.td134 /// FNEG {
179 /// } FNEG
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1002 FNEG, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp951 { ISD::FNEG, MVT::v8f64, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
966 { ISD::FNEG, MVT::v16f32, { 1, 1, 1, 2 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1153 { ISD::FNEG, MVT::v4f64, { 1, 1, 1, 2 } }, // vxorpd in getArithmeticInstrCost()
1154 { ISD::FNEG, MVT::v8f32, { 1, 1, 1, 2 } }, // vxorps in getArithmeticInstrCost()
1255 { ISD::FNEG, MVT::v4f64, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/ in getArithmeticInstrCost()
1256 { ISD::FNEG, MVT::v8f32, { 2, 2, 1, 2 } }, // BTVER2 from http://www.agner.org/ in getArithmeticInstrCost()
1401 { ISD::FNEG, MVT::f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1402 { ISD::FNEG, MVT::f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1403 { ISD::FNEG, MVT::v4f32, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
1404 { ISD::FNEG, MVT::v2f64, { 1, 1, 1, 1 } }, // Pentium IV from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1790 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1888 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1891 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1902 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
2888 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
3031 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3143 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp2000 case ISD::FNEG: return visitFNEG(N); in visit()
11847 return DAG.getNode(ISD::FNEG, DL, VT, Combined); in combineMinNumMaxNum()
16378 FPOpcode = ISD::FNEG; in foldBitcastedFPLogic()
16414 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, FPOp); in foldBitcastedFPLogic()
16528 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) || in visitBITCAST()
16541 if (N0.getOpcode() == ISD::FNEG) { in visitBITCAST()
16560 if (N0.getOpcode() == ISD::FNEG) in visitBITCAST()
17157 matcher.getNode(ISD::FNEG, SL, VT, Z)); in visitFSUBForFMACombine()
17168 matcher.getNode(ISD::FNEG, SL, VT, YZ.getOperand(0)), in visitFSUBForFMACombine()
17194 if (matcher.match(N0, ISD::FNEG) && isContractableFMUL(N0.getOperand(0)) && in visitFSUBForFMACombine()
[all …]
H A DLegalizeFloatTypes.cpp120 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; in SoftenFloatResult()
1601 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break; in ExpandFloatResult()
1727 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo), in ExpandFloatRes_FABS()
1966 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo); in ExpandFloatRes_FNEG()
1967 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi); in ExpandFloatRes_FNEG()
2847 case ISD::FNEG: in PromoteFloatResult()
3332 case ISD::FNEG: in SoftPromoteHalfResult()
H A DSelectionDAGBuilder.h543 void visitFNeg(const User &I) { visitUnary(I, ISD::FNEG); } in visitFNeg()
H A DLegalizeVectorOps.cpp403 case ISD::FNEG: in LegalizeOp()
1020 case ISD::FNEG: in Expand()
2009 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandFSUB()
H A DSelectionDAGDumper.cpp218 case ISD::FNEG: return "fneg"; in getOperationName()
H A DLegalizeDAG.cpp1715 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) { in ExpandFCOPYSIGN()
1717 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue); in ExpandFCOPYSIGN()
3722 case ISD::FNEG: in ExpandNode()
3892 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) { in ExpandNode()
3894 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); in ExpandNode()
4519 SDValue Neg = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(2), Flags); in ExpandNode()
5798 case ISD::FNEG: in PromoteNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td586 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)v2f32$")>;
612 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(FABS|FNEG)(v2f64|v4f32)$")>;
1117 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(FABS|FNEG)(S|D)r$")>;
H A DAArch64SchedCyclone.td436 // FABS,FNEG are WriteF
H A DAArch64SchedExynosM3.td545 def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td161 defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp205 setOperationAction(ISD::FNEG, VT, Legal); in XtensaTargetLowering()
212 setOperationAction(ISD::FNEG, VT, Expand); in XtensaTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td190 (instregex "FNEG(D|S)$"),
1058 (instregex "FNEG(D|S)_rec$"),
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td120 defm FNEG : FT_XZ<0b000111, "fneg", UnOpFrag<(fneg node:$Src)>>;
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def340 VP_PROPERTY_FUNCTIONAL_SDOPC(FNEG)
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp883 setOperationAction(ISD::FNEG, VT, in NVPTXTargetLowering()
886 setBF16OperationAction(ISD::FNEG, MVT::bf16, Legal, Expand); in NVPTXTargetLowering()
887 setBF16OperationAction(ISD::FNEG, MVT::v2bf16, Legal, Expand); in NVPTXTargetLowering()
888 setOperationAction(ISD::FNEG, MVT::v2f32, Expand); in NVPTXTargetLowering()

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