| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 85 DAG_FUNCTION(log2, 1, 1, experimental_constrained_log2, FLOG2)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1028 FLOG2, enumerator
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| H A D | BasicTTIImpl.h | 2301 ISD = ISD::FLOG2; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 266 case ISD::FLOG2: return "flog2"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 111 case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break; in SoftenFloatResult()
1592 case ISD::FLOG2: ExpandFloatRes_FLOG2(N, Lo, Hi); break; in ExpandFloatResult()
2844 case ISD::FLOG2: in PromoteFloatResult()
3329 case ISD::FLOG2: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 429 case ISD::FLOG2: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 106 case ISD::FLOG2: in ScalarizeVectorResult()
1228 case ISD::FLOG2: in SplitVectorResult()
4912 case ISD::FLOG2: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4772 case ISD::FLOG2: in ConvertNodeToLibcall()
5810 case ISD::FLOG2: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5789 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op, Flags); in expandLog2()
9523 if (visitUnaryFloatCall(I, ISD::FLOG2)) in visitCall()
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| H A D | SelectionDAG.cpp | 5789 case ISD::FLOG2: in isKnownNeverNaN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 399 setOperationAction(ISD::FLOG2, MVT::f32, Custom); in AMDGPUTargetLowering()
419 setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Legal); in AMDGPUTargetLowering()
422 setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Custom); in AMDGPUTargetLowering()
546 ISD::FEXP10, ISD::FLOG2, ISD::FREM, in AMDGPUTargetLowering()
1447 case ISD::FLOG2: in LowerOperation()
1485 case ISD::FLOG2: in ReplaceNodeResults()
2855 VT == MVT::f32 ? (unsigned)AMDGPUISD::LOG : (unsigned)ISD::FLOG2; in LowerFLOGUnsafe()
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| H A D | AMDGPUISelDAGToDAG.cpp | 151 case ISD::FLOG2: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 220 ISD::FLDEXP, ISD::FFREXP, ISD::FLOG, ISD::FLOG2, in SITargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 190 setOperationAction(ISD::FLOG2, MVT::f16, Promote); in MipsSETargetLowering()
427 setOperationAction(ISD::FLOG2, Ty, Legal); in addMSAFloatType()
1938 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsISelLowering.cpp | 465 setOperationAction(ISD::FLOG2, MVT::f32, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 1018 setOperationAction(ISD::FLOG2, MVT::f32, Legal); in NVPTXTargetLowering()
1019 setOperationPromotedToType(ISD::FLOG2, MVT::f16, MVT::f32); in NVPTXTargetLowering()
1020 setOperationPromotedToType(ISD::FLOG2, MVT::bf16, MVT::f32); in NVPTXTargetLowering()
1021 setOperationAction(ISD::FLOG2, {MVT::v2f16, MVT::v2bf16, MVT::v2f32}, in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 810 ISD::FLOG, ISD::FLOG2, in initActions()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 568 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 286 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 392 setOperationAction(ISD::FLOG2, VT, Expand); in addMVEVectorTypes()
875 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); in ARMTargetLowering()
898 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand); in ARMTargetLowering()
917 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand); in ARMTargetLowering()
1066 setOperationAction(ISD::FLOG2, MVT::f64, Expand); in ARMTargetLowering()
1512 setOperationAction(ISD::FLOG2, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1724 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 755 ISD::FEXP10, ISD::FLOG, ISD::FLOG2, in AArch64TargetLowering()
1241 ISD::FPOW, ISD::FLOG, ISD::FLOG2, in AArch64TargetLowering()
1735 setOperationAction(ISD::FLOG2, VT, Expand); in AArch64TargetLowering()
2020 setOperationAction(ISD::FLOG2, VT, Expand); in addTypeForNEON()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 538 ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2, in RISCVTargetLowering()
775 ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2, ISD::FLOG10}; in RISCVTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 867 setOperationAction(ISD::FLOG2, VT, Expand); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 624 setOperationAction(ISD::FLOG2, VT, Action); in X86TargetLowering()
957 setOperationAction(ISD::FLOG2, MVT::f80, Expand); in X86TargetLowering()
978 setOperationAction(ISD::FLOG2, VT, Expand); in X86TargetLowering()
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