| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 83 DAG_FUNCTION(log10, 1, 1, experimental_constrained_log10, FLOG10)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 983 FLOG10, enumerator
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| H A D | BasicTTIImpl.h | 2013 ISD = ISD::FLOG10; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 252 case ISD::FLOG10: return "flog10"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 107 case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break; in SoftenFloatResult()
1437 case ISD::FLOG10: ExpandFloatRes_FLOG10(N, Lo, Hi); break; in ExpandFloatResult()
2611 case ISD::FLOG10: in PromoteFloatResult()
3052 case ISD::FLOG10: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 416 case ISD::FLOG10: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 103 case ISD::FLOG10: in ScalarizeVectorResult()
1179 case ISD::FLOG10: in SplitVectorResult()
4541 case ISD::FLOG10: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4585 case ISD::FLOG10: in ConvertNodeToLibcall()
5552 case ISD::FLOG10: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5787 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op, Flags); in expandLog10()
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| H A D | SelectionDAG.cpp | 5452 case ISD::FLOG10: in isKnownNeverNaN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 402 {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32, in AMDGPUTargetLowering()
418 setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16, in AMDGPUTargetLowering()
534 ISD::FLOG, ISD::FLOG10, ISD::FPOW, in AMDGPUTargetLowering()
1393 case ISD::FLOG10: in LowerOperation()
1433 case ISD::FLOG10: in ReplaceNodeResults()
2697 const bool IsLog10 = Op.getOpcode() == ISD::FLOG10; in LowerFLOGCommon()
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| H A D | AMDGPUISelDAGToDAG.cpp | 156 case ISD::FLOG10: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 214 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10, in SITargetLowering()
476 setOperationAction({ISD::FLOG, ISD::FEXP, ISD::FLOG10}, MVT::f16, Custom); in SITargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 827 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 262 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 383 setOperationAction(ISD::FLOG10, VT, Expand); in addMVEVectorTypes()
886 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); in ARMTargetLowering()
909 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand); in ARMTargetLowering()
927 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand); in ARMTargetLowering()
1069 setOperationAction(ISD::FLOG10, MVT::f64, Expand); in ARMTargetLowering()
1552 setOperationAction(ISD::FLOG10, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1506 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP, in HexagonTargetLowering()
1656 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 152 setOperationAction(ISD::FLOG10, MVT::f16, Promote); in MipsSETargetLowering()
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| H A D | MipsISelLowering.cpp | 458 setOperationAction(ISD::FLOG10, MVT::f32, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 417 setOperationAction(ISD::FLOG10, MVT::f64, Custom); in PPCTargetLowering()
423 setOperationAction(ISD::FLOG10, MVT::f32, Custom); in PPCTargetLowering()
857 setOperationAction(ISD::FLOG10, VT, Expand); in PPCTargetLowering()
11800 case ISD::FLOG10: return lowerLog10(Op, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 741 ISD::FLOG10, ISD::STRICT_FREM, ISD::STRICT_FPOW, in AArch64TargetLowering()
1192 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, in AArch64TargetLowering()
1641 setOperationAction(ISD::FLOG10, VT, Expand); in AArch64TargetLowering()
1852 setOperationAction(ISD::FLOG10, VT, Expand); in addTypeForNEON()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 508 ISD::FLOG10}, in RISCVTargetLowering()
1003 setOperationAction(ISD::FLOG10, VT, Expand); in RISCVTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 618 setOperationAction(ISD::FLOG10, VT, Action); in X86TargetLowering()
945 setOperationAction(ISD::FLOG10, MVT::f80, Expand); in X86TargetLowering()
966 setOperationAction(ISD::FLOG10, VT, Expand); in X86TargetLowering()
2488 ISD::FLOG10, ISD::STRICT_FLOG10, in X86TargetLowering()
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