| /freebsd/contrib/one-true-awk/ |
| H A D | awk.h | 146 #define FLOG 4 macro
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| H A D | lex.c | 74 { "log", FLOG, BLTIN },
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| H A D | run.c | 2082 case FLOG: in bltin()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 82 DAG_FUNCTION(log, 1, 1, experimental_constrained_log, FLOG)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 981 FLOG, enumerator
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| H A D | BasicTTIImpl.h | 2010 ISD = ISD::FLOG; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 248 case ISD::FLOG: return "flog"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 103 case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break; in SoftenFloatResult()
1433 case ISD::FLOG: ExpandFloatRes_FLOG(N, Lo, Hi); break; in ExpandFloatResult()
2609 case ISD::FLOG: in PromoteFloatResult()
3050 case ISD::FLOG: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 414 case ISD::FLOG: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 102 case ISD::FLOG: in ScalarizeVectorResult()
1178 case ISD::FLOG: in SplitVectorResult()
4540 case ISD::FLOG: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4575 case ISD::FLOG: in ConvertNodeToLibcall()
5550 case ISD::FLOG: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5600 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op, Flags); in expandLog()
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| H A D | SelectionDAG.cpp | 5450 case ISD::FLOG: in isKnownNeverNaN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 402 {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32, in AMDGPUTargetLowering()
418 setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16, in AMDGPUTargetLowering()
534 ISD::FLOG, ISD::FLOG10, ISD::FPOW, in AMDGPUTargetLowering()
1392 case ISD::FLOG: in LowerOperation()
1432 case ISD::FLOG: in ReplaceNodeResults()
2698 assert(IsLog10 || Op.getOpcode() == ISD::FLOG); in LowerFLOGCommon()
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| H A D | AMDGPUISelDAGToDAG.cpp | 154 case ISD::FLOG: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 213 ISD::FLDEXP, ISD::FFREXP, ISD::FLOG, ISD::FLOG2, in SITargetLowering()
476 setOperationAction({ISD::FLOG, ISD::FEXP, ISD::FLOG10}, MVT::f16, Custom); in SITargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 827 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 262 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 381 setOperationAction(ISD::FLOG, VT, Expand); in addMVEVectorTypes()
884 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); in ARMTargetLowering()
907 setOperationAction(ISD::FLOG, MVT::v4f32, Expand); in ARMTargetLowering()
925 setOperationAction(ISD::FLOG, MVT::v2f32, Expand); in ARMTargetLowering()
1067 setOperationAction(ISD::FLOG, MVT::f64, Expand); in ARMTargetLowering()
1551 setOperationAction(ISD::FLOG, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1506 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP, in HexagonTargetLowering()
1655 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 150 setOperationAction(ISD::FLOG, MVT::f16, Promote); in MipsSETargetLowering()
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| H A D | MipsISelLowering.cpp | 456 setOperationAction(ISD::FLOG, MVT::f32, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 416 setOperationAction(ISD::FLOG, MVT::f64, Custom); in PPCTargetLowering()
422 setOperationAction(ISD::FLOG, MVT::f32, Custom); in PPCTargetLowering()
856 setOperationAction(ISD::FLOG, VT, Expand); in PPCTargetLowering()
11799 case ISD::FLOG: return lowerLog(Op, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 740 ISD::FEXP10, ISD::FLOG, ISD::FLOG2, in AArch64TargetLowering()
1191 ISD::FPOW, ISD::FLOG, ISD::FLOG2, in AArch64TargetLowering()
1639 setOperationAction(ISD::FLOG, VT, Expand); in AArch64TargetLowering()
1850 setOperationAction(ISD::FLOG, VT, Expand); in addTypeForNEON()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 507 ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2, in RISCVTargetLowering()
1001 setOperationAction(ISD::FLOG, VT, Expand); in RISCVTargetLowering()
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