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Searched refs:FIOp (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp209 int SPAdj, unsigned FIOp, in eliminateFrameIndex() argument
224 int FI = MI.getOperand(FIOp).getIndex(); in eliminateFrameIndex()
229 int RealOffset = Offset + MI.getOperand(FIOp+1).getImm(); in eliminateFrameIndex()
235 MI.getOperand(FIOp).ChangeToImmediate(RealOffset); in eliminateFrameIndex()
236 MI.removeOperand(FIOp+1); in eliminateFrameIndex()
347 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, false); in eliminateFrameIndex()
348 MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset); in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp895 MachineOperand *FIOp = in resolveFrameIndex() local
902 assert(FIOp && FIOp->isFI() && "frame index must be address operand"); in resolveFrameIndex()
909 FIOp->ChangeToRegister(BaseReg, false); in resolveFrameIndex()
921 FIOp->ChangeToRegister(BaseReg, false); in resolveFrameIndex()
2089 MachineOperand &FIOp = MI->getOperand(FIOperandNum); in eliminateFrameIndex() local
2285 FIOp.ChangeToRegister(FrameReg, false); in eliminateFrameIndex()
2338 FIOp.ChangeToImmediate(Offset); in eliminateFrameIndex()
2339 if (TII->isImmOperandLegal(*MI, FIOperandNum, FIOp)) in eliminateFrameIndex()
2345 FIOp.ChangeToRegister(AMDGPU::M0, false); in eliminateFrameIndex()
2346 bool UseSGPR = TII->isOperandLegal(*MI, FIOperandNum, &FIOp); in eliminateFrameIndex()
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H A DSIFrameLowering.cpp1376 unsigned FIOp = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in processFunctionBeforeFrameFinalized() local
1378 int FI = MI.getOperand(FIOp).getIndex(); in processFunctionBeforeFrameFinalized()
1386 TRI->eliminateFrameIndex(MI, 0, FIOp, RS); in processFunctionBeforeFrameFinalized()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4112 virtual void computeKnownBitsForFrameIndex(int FIOp,