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Searched refs:FGR64RegClass (Results 1 – 8 of 8) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()
69 const MCRegisterClass *FGR64RegClass; variable
H A DMipsSEInstrInfo.cpp147 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
156 else if (Mips::FGR64RegClass.contains(SrcReg)) in copyPhysReg()
164 else if (Mips::FGR64RegClass.contains(DestReg)) in copyPhysReg()
240 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
318 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
H A DMipsRegisterInfo.cpp187 for (MCPhysReg Reg : Mips::FGR64RegClass) in getReservedRegs()
H A DMipsSEFrameLowering.cpp319 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()
384 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()
478 } else if (Mips::FGR64RegClass.contains(Reg)) { in emitPrologue()
H A DMipsInstructionSelector.cpp137 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in getRegClassForTypeOnBank()
H A DMipsSEISelLowering.cpp169 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering()
3785 ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass) in emitFPEXTEND_PSEUDO()
H A DMipsISelLowering.cpp4174 return std::make_pair(0U, &Mips::FGR64RegClass); in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp84 FGR64RegClass->contains(SubReg) || in SetPhysRegUsed()