Searched refs:FGR32RegClass (Results 1 – 8 of 8) sorted by relevance
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); in MipsRegInfoRecord()68 const MCRegisterClass *FGR32RegClass; variable
98 else if (Mips::FGR32RegClass.contains(SrcReg)) in copyPhysReg()121 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()143 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()236 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()314 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
389 const TargetRegisterClass *RC = &Mips::FGR32RegClass; in materializeFP()773 ResultReg = createResultReg(&Mips::FGR32RegClass); in emitLoad()1029 RC = &Mips::FGR32RegClass; in selectSelect()1080 Register DestReg = createResultReg(&Mips::FGR32RegClass); in selectFPTrunc()1119 Register TempReg = createResultReg(&Mips::FGR32RegClass); in selectFPToInt()1420 Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++); in fastLowerArguments()
339 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8; in printSavedRegsBitmask()350 if (Mips::FGR32RegClass.contains(Reg)) { in printSavedRegsBitmask()
136 return &Mips::FGR32RegClass; in getRegClassForTypeOnBank()645 Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass); in select()
164 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); in MipsSETargetLowering()
4171 return std::make_pair(0U, &Mips::FGR32RegClass); in getRegForInlineAsmConstraint()
83 else if (FGR32RegClass->contains(SubReg) || in SetPhysRegUsed()