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Searched refs:FFLOOR (Results 1 – 25 of 35) sorted by relevance

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/freebsd/lib/msun/src/
H A Ds_cospi.c107 FFLOOR(x, j0, ix, lx); /* Integer part of ax. */ in cospi()
H A Ds_sinpi.c121 FFLOOR(x, j0, ix, lx); /* Integer part of ax. */ in sinpi()
H A Ds_tanpi.c146 FFLOOR(x, j0, ix, lx); /* Integer part of ax. */ in tanpi()
H A Dmath_private.h783 #define FFLOOR(x, j0, ix, lx) do { \ macro
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp87 case ISD::FFLOOR: in hasNativeBF16Support()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def81 DAG_FUNCTION(floor, 1, 0, experimental_constrained_floor, FFLOOR)
H A DVPIntrinsics.def413 VP_PROPERTY_FUNCTIONAL_SDOPC(FFLOOR)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1039 FFLOOR, enumerator
H A DBasicTTIImpl.h2334 ISD = ISD::FFLOOR; in getTypeBasedIntrinsicInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp247 case ISD::FFLOOR: return "ffloor"; in getOperationName()
H A DLegalizeFloatTypes.cpp107 case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break; in SoftenFloatResult()
1588 case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break; in ExpandFloatResult()
2842 case ISD::FFLOOR: in PromoteFloatResult()
3327 case ISD::FFLOOR: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp440 case ISD::FFLOOR: in LegalizeOp()
1300 case ISD::FFLOOR: in Expand()
H A DLegalizeVectorTypes.cpp103 case ISD::FFLOOR: in ScalarizeVectorResult()
1224 case ISD::FFLOOR: in SplitVectorResult()
4909 case ISD::FFLOOR: in WidenVectorResult()
H A DLegalizeDAG.cpp4802 case ISD::FFLOOR: in ConvertNodeToLibcall()
5791 case ISD::FFLOOR: in PromoteNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp376 setOperationAction(ISD::FFLOOR, VT, Legal); in addMVEVectorTypes()
885 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); in ARMTargetLowering()
908 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand); in ARMTargetLowering()
927 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand); in ARMTargetLowering()
929 for (ISD::NodeType Op : {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in ARMTargetLowering()
1076 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); in ARMTargetLowering()
1468 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in ARMTargetLowering()
1485 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in ARMTargetLowering()
1519 setOperationAction(ISD::FFLOOR, MVT::f16, Legal); in ARMTargetLowering()
1536 setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal); in ARMTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp394 setOperationAction({ISD::FCEIL, ISD::FPOW, ISD::FABS, ISD::FFLOOR, in AMDGPUTargetLowering()
548 ISD::FFLOOR, ISD::FTRUNC, ISD::FMUL, in AMDGPUTargetLowering()
1446 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); in LowerOperation()
3553 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul); in LowerFP_TO_INT64()
H A DR600ISelLowering.cpp108 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR}, in R600TargetLowering()
H A DAMDGPUISelDAGToDAG.cpp161 case ISD::FFLOOR: in fp16SrcZerosHighBits()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp813 ISD::FFLOOR, ISD::FNEARBYINT, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp330 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); in PPCTargetLowering()
468 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
473 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
873 setOperationAction(ISD::FFLOOR, VT, Expand); in PPCTargetLowering()
937 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
1043 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
1254 setOperationAction(ISD::FFLOOR, MVT::f128, Legal); in PPCTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1254 case ISD::FFLOOR: in PreprocessISelDAG()
1272 case ISD::FFLOOR: Imm = 0x9; break; in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp798 ISD::FFLOOR, in AArch64TargetLowering()
848 setOperationPromotedToType(ISD::FFLOOR, V4Narrow, MVT::v4f32); in AArch64TargetLowering()
875 setOperationAction(ISD::FFLOOR, V8Narrow, Legal); in AArch64TargetLowering()
902 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in AArch64TargetLowering()
1237 ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT, in AArch64TargetLowering()
1403 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1695 setOperationAction(ISD::FFLOOR, VT, Custom); in AArch64TargetLowering()
1781 {ISD::FCEIL, ISD::FDIV, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT, in AArch64TargetLowering()
2291 setOperationAction(ISD::FFLOOR, VT, Default); in addTypeForFixedLengthSVE()
7292 case ISD::FFLOOR: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp471 ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FRINT, ISD::FROUND, in RISCVTargetLowering()
481 ISD::SETCC, ISD::FCEIL, ISD::FFLOOR, in RISCVTargetLowering()
1018 ISD::FFLOOR, in RISCVTargetLowering()
1084 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND, in RISCVTargetLowering()
1515 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND, in RISCVTargetLowering()
3215 case ISD::FFLOOR: in matchRoundingOp()
3315 case ISD::FFLOOR: in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
7719 case ISD::FFLOOR: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td573 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp141 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()

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