| /freebsd/lib/msun/src/ |
| H A D | s_cospi.c | 107 FFLOOR(x, j0, ix, lx); /* Integer part of ax. */ in cospi()
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| H A D | s_sinpi.c | 121 FFLOOR(x, j0, ix, lx); /* Integer part of ax. */ in sinpi()
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| H A D | s_tanpi.c | 146 FFLOOR(x, j0, ix, lx); /* Integer part of ax. */ in tanpi()
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| H A D | math_private.h | 700 #define FFLOOR(x, j0, ix, lx) do { \ macro
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 80 DAG_FUNCTION(floor, 1, 0, experimental_constrained_floor, FFLOOR)
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| H A D | VPIntrinsics.def | 440 VP_PROPERTY_FUNCTIONAL_SDOPC(FFLOOR)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 993 FFLOOR, enumerator
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| H A D | BasicTTIImpl.h | 2040 ISD = ISD::FFLOOR; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 231 case ISD::FFLOOR: return "ffloor"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 101 case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break; in SoftenFloatResult()
1431 case ISD::FFLOOR: ExpandFloatRes_FFLOOR(N, Lo, Hi); break; in ExpandFloatResult()
2608 case ISD::FFLOOR: in PromoteFloatResult()
3049 case ISD::FFLOOR: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 426 case ISD::FFLOOR: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 101 case ISD::FFLOOR: in ScalarizeVectorResult()
1176 case ISD::FFLOOR: in SplitVectorResult()
4539 case ISD::FFLOOR: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4610 case ISD::FFLOOR: in ConvertNodeToLibcall()
5532 case ISD::FFLOOR: in PromoteNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 394 setOperationAction({ISD::FCEIL, ISD::FPOW, ISD::FABS, ISD::FFLOOR, in AMDGPUTargetLowering()
535 ISD::FFLOOR, ISD::FTRUNC, ISD::FMUL, in AMDGPUTargetLowering()
1389 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG); in LowerOperation()
3495 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, SrcVT, Mul); in LowerFP_TO_INT64()
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| H A D | R600ISelLowering.cpp | 104 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR}, in R600TargetLowering()
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| H A D | AMDGPUISelDAGToDAG.cpp | 165 case ISD::FFLOOR: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 828 ISD::FEXP, ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 322 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); in PPCTargetLowering()
460 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
465 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
864 setOperationAction(ISD::FFLOOR, VT, Expand); in PPCTargetLowering()
928 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
1026 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
1236 setOperationAction(ISD::FFLOOR, MVT::f128, Legal); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 447 ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FRINT, ISD::FROUND, in RISCVTargetLowering()
460 ISD::SETCC, ISD::FCEIL, ISD::FFLOOR, in RISCVTargetLowering()
950 ISD::FFLOOR, ISD::FROUND, ISD::FROUNDEVEN, ISD::FRINT, in RISCVTargetLowering()
985 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND, in RISCVTargetLowering()
1374 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND, in RISCVTargetLowering()
3016 case ISD::FFLOOR: in matchRoundingOp()
3035 // Expand vector FTRUNC, FCEIL, FFLOOR, FROUND, VP_FCEIL, VP_FFLOOR, VP_FROUND
3102 case ISD::FFLOOR: in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
6766 case ISD::FFLOOR: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1210 case ISD::FFLOOR: in PreprocessISelDAG()
1228 case ISD::FFLOOR: Imm = 0x9; break; in PreprocessISelDAG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 136 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 451 case ISD::FFLOOR: in NVPTXTargetLowering()
769 for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT, in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 767 ISD::FFLOOR, in AArch64TargetLowering()
814 setOperationPromotedToType(ISD::FFLOOR, V4Narrow, MVT::v4f32); in AArch64TargetLowering()
837 setOperationAction(ISD::FFLOOR, V8Narrow, Legal); in AArch64TargetLowering()
864 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in AArch64TargetLowering()
1187 ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT, in AArch64TargetLowering()
1349 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1601 setOperationAction(ISD::FFLOOR, VT, Custom); in AArch64TargetLowering()
2055 setOperationAction(ISD::FFLOOR, VT, Default); in addTypeForFixedLengthSVE()
6825 case ISD::FFLOOR: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 520 setOperationAction(ISD::FFLOOR, VT, Legal); in SystemZTargetLowering()
580 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in SystemZTargetLowering()
621 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in SystemZTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 542 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
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