| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXSubtarget.cpp | 85 case ISD::FEXP2: in hasNativeBF16Support()
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| H A D | NVPTXISelLowering.cpp | 551 case ISD::FEXP2: in NVPTXTargetLowering()
1008 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in NVPTXTargetLowering()
1009 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in NVPTXTargetLowering()
1010 setFP16OperationAction(ISD::FEXP2, MVT::f16, Legal, Promote); in NVPTXTargetLowering()
1011 setFP16OperationAction(ISD::FEXP2, MVT::v2f16, Legal, Expand); in NVPTXTargetLowering()
1012 setBF16OperationAction(ISD::FEXP2, MVT::bf16, Legal, Promote); in NVPTXTargetLowering()
1013 setBF16OperationAction(ISD::FEXP2, MVT::v2bf16, Legal, Expand); in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 80 DAG_FUNCTION(exp2, 1, 1, experimental_constrained_exp2, FEXP2)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1031 FEXP2, enumerator
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| H A D | BasicTTIImpl.h | 2289 ISD = ISD::FEXP2; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 405 {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32, in AMDGPUTargetLowering()
419 setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Legal); in AMDGPUTargetLowering()
422 setOperationAction({ISD::FLOG2, ISD::FEXP2}, MVT::f16, Custom); in AMDGPUTargetLowering()
545 ISD::FDIV, ISD::FEXP2, ISD::FEXP, in AMDGPUTargetLowering()
1455 case ISD::FEXP2: in LowerOperation()
1494 case ISD::FEXP2: in ReplaceNodeResults()
2950 : (unsigned)ISD::FEXP2, in lowerFEXPUnsafe()
2985 : static_cast<unsigned>(ISD::FEXP2); in lowerFEXP10Unsafe()
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| H A D | AMDGPUISelDAGToDAG.cpp | 154 case ISD::FEXP2: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 221 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10, in SITargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 812 ISD::FEXP2, ISD::FEXP10, in initActions()
1924 return ISD::FEXP2; in IntrinsicIDToISD()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 261 case ISD::FEXP2: return "fexp2"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 104 case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break; in SoftenFloatResult()
1585 case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break; in ExpandFloatResult()
2840 case ISD::FEXP2: in PromoteFloatResult()
3325 case ISD::FEXP2: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 432 case ISD::FEXP2: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 101 case ISD::FEXP2: in ScalarizeVectorResult()
1222 case ISD::FEXP2: in SplitVectorResult()
4907 case ISD::FEXP2: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4787 case ISD::FEXP2: in ConvertNodeToLibcall()
5814 case ISD::FEXP2: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5891 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op, Flags); in expandExp2()
9529 if (visitUnaryFloatCall(I, ISD::FEXP2)) in visitCall()
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| H A D | SelectionDAG.cpp | 5752 case ISD::FEXP2: in isKnownNeverNaN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 188 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in MipsSETargetLowering()
426 setOperationAction(ISD::FEXP2, Ty, Legal); in addMSAFloatType()
1934 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsMSAInstrInfo.td | 1977 // 1.0 when we only need to match ISD::FEXP2.
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 565 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 287 ISD::FEXP, ISD::FEXP2}) in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 395 setOperationAction(ISD::FEXP2, VT, Expand); in addMVEVectorTypes()
878 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); in ARMTargetLowering()
901 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); in ARMTargetLowering()
920 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in ARMTargetLowering()
1069 setOperationAction(ISD::FEXP2, MVT::f64, Expand); in ARMTargetLowering()
1508 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1725 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 754 ISD::FTAN, ISD::FEXP, ISD::FEXP2, in AArch64TargetLowering()
1242 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, in AArch64TargetLowering()
1732 setOperationAction(ISD::FEXP2, VT, Expand); in AArch64TargetLowering()
2023 setOperationAction(ISD::FEXP2, VT, Expand); in addTypeForNEON()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 538 ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2, in RISCVTargetLowering()
775 ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2, ISD::FLOG10}; in RISCVTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 869 setOperationAction(ISD::FEXP2, VT, Expand); in PPCTargetLowering()
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