| /freebsd/contrib/one-true-awk/ |
| H A D | awk.h | 145 #define FEXP 3 macro
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| H A D | lex.c | 61 { "exp", FEXP, BLTIN },
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| H A D | run.c | 2090 case FEXP: in bltin()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 79 DAG_FUNCTION(exp, 1, 1, experimental_constrained_exp, FEXP)
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| H A D | RuntimeLibcalls.td | 2215 def zos___FEXP_B : RuntimeLibcallImpl<EXP_F32, "@@FEXP@B">;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1030 FEXP, enumerator
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| H A D | BasicTTIImpl.h | 2286 ISD = ISD::FEXP; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 811 ISD::FLOG10, ISD::FEXP, in initActions()
1922 return ISD::FEXP; in IntrinsicIDToISD()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 259 case ISD::FEXP: return "fexp"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 102 case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break; in SoftenFloatResult()
1583 case ISD::FEXP: ExpandFloatRes_FEXP(N, Lo, Hi); break; in ExpandFloatResult()
2839 case ISD::FEXP: in PromoteFloatResult()
3324 case ISD::FEXP: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 431 case ISD::FEXP: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 100 case ISD::FEXP: in ScalarizeVectorResult()
1221 case ISD::FEXP: in SplitVectorResult()
4906 case ISD::FEXP: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4782 case ISD::FEXP: in ConvertNodeToLibcall()
5813 case ISD::FEXP: in PromoteNode()
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| H A D | SelectionDAGBuilder.cpp | 5593 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op, Flags); in expandExp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 405 {ISD::FLOG, ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10}, MVT::f32, in AMDGPUTargetLowering()
425 setOperationAction({ISD::FLOG10, ISD::FLOG, ISD::FEXP, ISD::FEXP10}, MVT::f16, in AMDGPUTargetLowering()
545 ISD::FDIV, ISD::FEXP2, ISD::FEXP, in AMDGPUTargetLowering()
1452 case ISD::FEXP: in LowerOperation()
1498 case ISD::FEXP: in ReplaceNodeResults()
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| H A D | AMDGPUISelDAGToDAG.cpp | 153 case ISD::FEXP: in fp16SrcZerosHighBits()
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| H A D | SIISelLowering.cpp | 221 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FEXP10, in SITargetLowering()
491 setOperationAction({ISD::FLOG, ISD::FEXP, ISD::FLOG10}, MVT::f16, Custom); in SITargetLowering()
835 setOperationAction(ISD::FEXP, MVT::v2f16, Custom); in SITargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 287 ISD::FEXP, ISD::FEXP2}) in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 394 setOperationAction(ISD::FEXP, VT, Expand); in addMVEVectorTypes()
877 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); in ARMTargetLowering()
900 setOperationAction(ISD::FEXP, MVT::v4f32, Expand); in ARMTargetLowering()
919 setOperationAction(ISD::FEXP, MVT::v2f32, Expand); in ARMTargetLowering()
1068 setOperationAction(ISD::FEXP, MVT::f64, Expand); in ARMTargetLowering()
1507 setOperationAction(ISD::FEXP, MVT::f16, Promote); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 187 setOperationAction(ISD::FEXP, MVT::f16, Promote); in MipsSETargetLowering()
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| H A D | MipsISelLowering.cpp | 467 setOperationAction(ISD::FEXP, MVT::f32, Expand); in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1725 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 426 setOperationAction(ISD::FEXP, MVT::f64, Custom); in PPCTargetLowering()
432 setOperationAction(ISD::FEXP, MVT::f32, Custom); in PPCTargetLowering()
868 setOperationAction(ISD::FEXP, VT, Expand); in PPCTargetLowering()
12548 case ISD::FEXP: return lowerExp(Op, DAG); in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 754 ISD::FTAN, ISD::FEXP, ISD::FEXP2, in AArch64TargetLowering()
1242 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, in AArch64TargetLowering()
1731 setOperationAction(ISD::FEXP, VT, Expand); in AArch64TargetLowering()
2022 setOperationAction(ISD::FEXP, VT, Expand); in addTypeForNEON()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 537 ISD::FCOS, ISD::FSIN, ISD::FSINCOS, ISD::FEXP, in RISCVTargetLowering()
774 ISD::FREM, ISD::FPOW, ISD::FCOS, ISD::FSIN, ISD::FSINCOS, ISD::FEXP, in RISCVTargetLowering()
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