Home
last modified time | relevance | path

Searched refs:FCVT (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedAmpere1.td876 def : InstRW<[Ampere1Write_4cyc_1XY], (instregex "^FCVT[AMNPZ][SU]v.[if]16")>;
905 def : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FCVT[AMNPZ][SU]v.[if](32|64)")>;
923 def : InstRW<[Ampere1Write_10cyc_1XY_1Z], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
924 def : InstRW<[Ampere1Write_5cyc_1XY], (instregex "^FCVT[HSD]Hr")>;
925 def : InstRW<[Ampere1Write_6cyc_1XY], (instregex "^FCVT[HSD][SD]r")>;
927 def : InstRW<[Ampere1Write_8cyc_2XY], (instregex "^FCVT(N|XN)v")>;
H A DAArch64SchedAmpere1B.td842 def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT[AMNPZ][SU]v.[if]16")>;
880 def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT[AMNPZ][SU]v.[if](32|64)")>;
905 def : InstRW<[Ampere1BWrite_7cyc_1XY_1Z], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
906 def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT[HSD]Hr")>;
907 def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT[HSD][SD]r")>;
909 def : InstRW<[Ampere1BWrite_3cyc_1XY], (instregex "^FCVT(N|XN)v")>;
H A DAArch64SchedTSV110.td515 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^FCVT(A|M|N|P|Z)(S|U)U(W|X)(S|D)r$")>;
516 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCVT[HSD][HSD]r")>;
641 def : InstRW<[TSV110Wr_2cyc_1F], (instregex "^FCVT[AMNPZ][SU]v")>;
642 def : InstRW<[TSV110Wr_3cyc_1F], (instregex "^FCVT(L)v")>;
643 def : InstRW<[TSV110Wr_5cyc_1F], (instregex "^FCVT(N|XN)v")>;
H A DAArch64SchedNeoverseV1.td791 def : InstRW<[V1Write_3c_1V0], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>;
1019 def : InstRW<[V1Write_3c_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",
1020 "^FCVT[AMNPZ][SU]v2i(32|64)_shift$",
1021 "^FCVT[AMNPZ][SU]v1i64$",
1029 def : InstRW<[V1Write_4c_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",
1030 "^FCVT[AMNPZ][SU]v4i(16|32)_shift$",
1031 "^FCVT[AMNPZ][SU]v1i32$",
1039 def : InstRW<[V1Write_6c_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$",
1040 "^FCVT[AMNPZ][SU]v8i16_shift$",
1041 "^FCVT[AMNPZ][SU]v1f16$",
H A DAArch64SchedCyclone.td575 // FCVT lengthen f16/s32
578 // FCVT,FCVTN,FCVTXN
585 def : InstRW<[CyWriteCopyToFPR], (instregex "FCVT[AMNPZ][SU][SU][WX][SD]r")>;
587 // FCVT Rd, S/D = V6+LD4: 10 cycles
H A DAArch64SchedExynosM4.td663 def : InstRW<[M4WriteFCVT2H], (instregex "^FCVT[SD]Hr")>;
664 def : InstRW<[M4WriteFCVT2], (instregex "^FCVT[SD][SD]r")>;
666 def : InstRW<[M4WriteNEONR], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
780 def : InstRW<[M4WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>;
781 def : InstRW<[M4WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
H A DAArch64SchedOryon.td518 // inline a FCVT, so add one more uOp
525 // Latency is 3, FCVT is also 3 cycle
532 // inline a FCVT, so add one more uOp
1376 def : InstRW<[ORYONWrite_V2I_6Cyc_FP01], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
1384 def : InstRW<[ORYONWrite_V2V_3Cyc_FP0123], (instregex "^FCVT[HSD][HSD]r",
1500 def : InstRW<[ORYONWrite_3Cyc_FP0123], (instregex "^FCVT(L|L2|N|N2|XN|XN2)v",
H A DAArch64SchedExynosM3.td552 def : InstRW<[M3WriteFCVT3], (instregex "^FCVT[DHS][DHS]r")>;
554 def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>;
646 def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>;
647 def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>;
H A DAArch64SchedNeoverseV2.td1338 (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]ri?$")>;
1580 def : InstRW<[V2Write_3c_1V02], (instregex "^FCVT[AMNPZ][SU]v2f(32|64)$",
1581 "^FCVT[AMNPZ][SU]v2i(32|64)_shift$",
1582 "^FCVT[AMNPZ][SU]v1i64$",
1590 def : InstRW<[V2Write_4c_2V02], (instregex "^FCVT[AMNPZ][SU]v4f(16|32)$",
1591 "^FCVT[AMNPZ][SU]v4i(16|32)_shift$",
1592 "^FCVT[AMNPZ][SU]v1i32$",
1600 def : InstRW<[V2Write_6c_4V02], (instregex "^FCVT[AMNPZ][SU]v8f16$",
1601 "^FCVT[AMNPZ][SU]v8i16_shift$",
1602 "^FCVT[AMNPZ][SU]v1f16$",
H A DAArch64SchedExynosM5.td721 def : InstRW<[M5WriteFCVT2], (instregex "^FCVT[HSD][HSD]r")>;
723 def : InstRW<[M5WriteFCVTB], (instregex "^FCVT[AMNPZ][SU][SU][XW][HSD]r")>;
823 def : InstRW<[M5WriteFCVT2], (instregex "^FCVT(L|N|XN)v")>;
824 def : InstRW<[M5WriteFCVT2A], (instregex "^FCVT[AMNPZ][SU]v")>;
H A DAArch64SchedA55.td368 def : InstRW<[CortexA55WriteFPALU_F3], (instregex "^FCVT[ALMNPZ][SU](S|U)?(W|X)")>;
369 def : InstRW<[CortexA55WriteFPALU_F4], (instregex "^FCVT(X)?[ALMNPXZ](S|U|N)?v")>;
H A DAArch64SchedFalkorDetails.td598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>;
624 def : InstRW<[FalkorWr_2VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v2f64|v4f32)$")>;
1116 def : InstRW<[FalkorWr_1VTOG_1cyc], (instregex "^FCVT(A|M|N|P|Z)(S|U)U(W|X)(S|D)r$")>;
H A DAArch64SchedKryoDetails.td729 (instregex "FCVT(((A|N|M|P)(S|U)(S|U)|Z(S|U)_Int(S|U))(W|X)(D|S)ri?|Z(S|U)(d|s))$")>;
735 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
741 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v4f32|v2f64)$")>;
H A DAArch64SchedA510.td378 def : InstRW<[CortexA510WriteFPALU_F4], (instregex "^FCVT[ALMNPZ][SU](S|U)?(W|X)")>;
379 def : InstRW<[CortexA510WriteFPALU_F4], (instregex "^FCVT(X)?[ALMNPXZ](S|U|N)?v")>;
H A DAArch64SchedA320.td400 def : InstRW<[CortexA320WriteFPALU_F4], (instregex "^FCVT[ALMNPZ][SU](S|U)?(W|X)")>;
401 def : InstRW<[CortexA320WriteFPALU_F4], (instregex "^FCVT(X)?[ALMNPXZ](S|U|N)?v")>;
H A DAArch64SchedA57.td461 def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>;
H A DAArch64SchedA64FX.td1571 def : InstRW<[A64FXWrite_FCVTXNV], (instregex "^FCVT(L|N|XN)v")>;
2087 "^FMUL_(ZP|ZZZ_)", "^FMULX_Z", "^FCVT(ZS|ZU)?_Z",
H A DAArch64SchedNeoverseN1.td453 def : InstRW<[N1Write_4c_1V0_1V1], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>;
H A DAArch64SchedThunderX2T99.td1426 def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^FCVT(L|N|XN)v")>;
H A DAArch64SchedThunderX3T110.td1534 def : InstRW<[THX3T110Write_5Cyc_F01], (instregex "^FCVT(L|N|XN)v")>;
H A DAArch64SchedNeoverseN2.td872 def : InstRW<[N2Write_3c_1V], (instregex "^FCVT[AMNPZ][SU][SU][WX][HSD]r$")>;
H A DAArch64InstrInfo.td5140 // AArch64's FCVT instructions saturate when out of range.
5375 defm FCVT : FPConversion<"fcvt">;
5762 // AArch64's FCVT instructions saturate when out of range.
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1618 unsigned FCVT = IsSigned ? RISCV::VFCVT_RTZ_X_F_V : RISCV::VFCVT_RTZ_XU_F_V; in getCastInstrCost() local
1642 Cost += getRISCVInstructionCost(FCVT, DstLT.second, CostKind); in getCastInstrCost()
1662 unsigned FCVT = IsSigned ? RISCV::VFCVT_F_X_V : RISCV::VFCVT_F_XU_V; in getCastInstrCost() local
1685 Cost += getRISCVInstructionCost(FCVT, DstLT.second, CostKind); in getCastInstrCost()