| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXSubtarget.cpp | 86 case ISD::FCEIL: in hasNativeBF16Support()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 76 DAG_FUNCTION(ceil, 1, 0, experimental_constrained_ceil, FCEIL)
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| H A D | VPIntrinsics.def | 407 VP_PROPERTY_FUNCTIONAL_SDOPC(FCEIL)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1033 FCEIL, enumerator
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| H A D | BasicTTIImpl.h | 2337 ISD = ISD::FCEIL; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 249 case ISD::FCEIL: return "fceil"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 93 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
1574 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
2836 case ISD::FCEIL: in PromoteFloatResult()
3321 case ISD::FCEIL: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 434 case ISD::FCEIL: in LegalizeOp()
1299 case ISD::FCEIL: in Expand()
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| H A D | LegalizeVectorTypes.cpp | 97 case ISD::FCEIL: in ScalarizeVectorResult()
1217 case ISD::FCEIL: in SplitVectorResult()
4903 case ISD::FCEIL: in WidenVectorResult()
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| H A D | LegalizeDAG.cpp | 4808 case ISD::FCEIL: in ConvertNodeToLibcall()
5792 case ISD::FCEIL: in PromoteNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 377 setOperationAction(ISD::FCEIL, VT, Legal); in addMVEVectorTypes()
880 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); in ARMTargetLowering()
903 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand); in ARMTargetLowering()
922 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand); in ARMTargetLowering()
929 for (ISD::NodeType Op : {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in ARMTargetLowering()
1071 setOperationAction(ISD::FCEIL, MVT::f64, Expand); in ARMTargetLowering()
1469 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in ARMTargetLowering()
1486 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in ARMTargetLowering()
1520 setOperationAction(ISD::FCEIL, MVT::f16, Legal); in ARMTargetLowering()
1542 setOperationAction(ISD::FCEIL, MVT::v2f32, Legal); in ARMTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 814 ISD::FCEIL, ISD::FRINT, in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 108 setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR}, in R600TargetLowering()
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| H A D | AMDGPUISelLowering.cpp | 394 setOperationAction({ISD::FCEIL, ISD::FPOW, ISD::FABS, ISD::FFLOOR, in AMDGPUTargetLowering()
544 ISD::FADD, ISD::FCEIL, ISD::FCOS, in AMDGPUTargetLowering()
1439 case ISD::FCEIL: return LowerFCEIL(Op, DAG); in LowerOperation()
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| H A D | AMDGPUISelDAGToDAG.cpp | 155 case ISD::FCEIL: in fp16SrcZerosHighBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 1267 if (!LT.second.isVector() && TLI->isOperationCustom(ISD::FCEIL, LT.second)) in getIntrinsicInstrCost()
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| H A D | RISCVISelLowering.cpp | 471 ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FRINT, ISD::FROUND, in RISCVTargetLowering()
481 ISD::SETCC, ISD::FCEIL, ISD::FFLOOR, in RISCVTargetLowering()
1016 ISD::FCEIL, in RISCVTargetLowering()
1084 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND, in RISCVTargetLowering()
1515 setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND, in RISCVTargetLowering()
3219 case ISD::FCEIL: in matchRoundingOp()
3313 case ISD::FCEIL: in lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
7718 case ISD::FCEIL: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 331 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
469 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
474 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
874 setOperationAction(ISD::FCEIL, VT, Expand); in PPCTargetLowering()
938 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
1044 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
1255 setOperationAction(ISD::FCEIL, MVT::f128, Legal); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1252 case ISD::FCEIL: in PreprocessISelDAG()
1270 case ISD::FCEIL: Imm = 0xA; break; in PreprocessISelDAG()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 796 ISD::FCEIL, in AArch64TargetLowering()
847 setOperationPromotedToType(ISD::FCEIL, V4Narrow, MVT::v4f32); in AArch64TargetLowering()
872 setOperationAction(ISD::FCEIL, V8Narrow, Legal); in AArch64TargetLowering()
902 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, in AArch64TargetLowering()
1236 ISD::FNEG, ISD::FABS, ISD::FCEIL, in AArch64TargetLowering()
1403 {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, in AArch64TargetLowering()
1694 setOperationAction(ISD::FCEIL, VT, Custom); in AArch64TargetLowering()
1781 {ISD::FCEIL, ISD::FDIV, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT, in AArch64TargetLowering()
2288 setOperationAction(ISD::FCEIL, VT, Default); in addTypeForFixedLengthSVE()
7290 case ISD::FCEIL: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 572 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 141 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 572 setOperationAction(ISD::FCEIL, VT, Legal); in SystemZTargetLowering()
637 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in SystemZTargetLowering()
680 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in SystemZTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 175 setOperationAction(ISD::FCEIL, MVT::f16, Promote); in MipsSETargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1725 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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