Searched refs:ExtractVT (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 17384 MVT ExtractVT = MVT::getVectorVT(MVT::i1, SubvecElts); in lower1BitShuffle() local
17385 SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtractVT, in lower1BitShuffle()
44285 EVT ExtractVT = Extract->getValueType(0); in combineMinMaxReduction() local
44286 if (ExtractVT != MVT::i16 && ExtractVT != MVT::i8) in combineMinMaxReduction()
44298 if (SrcSVT != ExtractVT || (SrcVT.getSizeInBits() % 128) != 0) in combineMinMaxReduction()
44311 assert(((SrcVT == MVT::v8i16 && ExtractVT == MVT::i16) || in combineMinMaxReduction()
44312 (SrcVT == MVT::v16i8 && ExtractVT == MVT::i8)) && in combineMinMaxReduction()
44318 unsigned MaskEltsBits = ExtractVT.getSizeInBits(); in combineMinMaxReduction()
44333 if (ExtractVT == MVT::i8) { in combineMinMaxReduction()
44348 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtractVT, MinPos, in combineMinMaxReduction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 16463 EVT ExtractVT = VT.getVectorElementType(); in PerformVDUPLANECombine() local
16465 if (!DCI.DAG.getTargetLoweringInfo().isTypeLegal(ExtractVT)) in PerformVDUPLANECombine()
16466 ExtractVT = MVT::i32; in PerformVDUPLANECombine()
16467 SDValue Extract = DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ExtractVT, in PerformVDUPLANECombine()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 24912 EVT ExtractVT = in visitEXTRACT_SUBVECTOR() local
24917 TLI.isOperationLegal(ISD::BUILD_VECTOR, ExtractVT))) && in visitEXTRACT_SUBVECTOR()
24918 (!LegalTypes || TLI.isTypeLegal(ExtractVT))) { in visitEXTRACT_SUBVECTOR()
24930 DAG.getBuildVector(ExtractVT, DL, V->ops().slice(IdxVal, NumElems)); in visitEXTRACT_SUBVECTOR()
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