17384     MVT ExtractVT = MVT::getVectorVT(MVT::i1, SubvecElts);  in lower1BitShuffle()  local
17385     SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtractVT,  in lower1BitShuffle()
44285   EVT ExtractVT = Extract->getValueType(0);  in combineMinMaxReduction()  local
44286   if (ExtractVT != MVT::i16 && ExtractVT != MVT::i8)  in combineMinMaxReduction()
44298   if (SrcSVT != ExtractVT || (SrcVT.getSizeInBits() % 128) != 0)  in combineMinMaxReduction()
44311   assert(((SrcVT == MVT::v8i16 && ExtractVT == MVT::i16) ||  in combineMinMaxReduction()
44312           (SrcVT == MVT::v16i8 && ExtractVT == MVT::i8)) &&  in combineMinMaxReduction()
44318   unsigned MaskEltsBits = ExtractVT.getSizeInBits();  in combineMinMaxReduction()
44333   if (ExtractVT == MVT::i8) {  in combineMinMaxReduction()
44348   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtractVT, MinPos,  in combineMinMaxReduction()
44359   EVT ExtractVT = Extract->getValueType(0);  in combinePredicateReduction()  local
44360   unsigned BitWidth = ExtractVT.getSizeInBits();  in combinePredicateReduction()
44361   if (ExtractVT != MVT::i64 && ExtractVT != MVT::i32 && ExtractVT != MVT::i16 &&  in combinePredicateReduction()
44362       ExtractVT != MVT::i8 && ExtractVT != MVT::i1)  in combinePredicateReduction()
44368   if (!Match && ExtractVT == MVT::i1)  in combinePredicateReduction()
44386   if (ExtractVT == MVT::i1) {  in combinePredicateReduction()
44402           return DAG.getNode(ISD::TRUNCATE, DL, ExtractVT,  in combinePredicateReduction()
44468     return DAG.getZExtOrTrunc(Result, DL, ExtractVT);  in combinePredicateReduction()
44488   SDValue Zext = DAG.getZExtOrTrunc(Setcc, DL, ExtractVT);  in combinePredicateReduction()
44489   return DAG.getNegative(Zext, DL, ExtractVT);  in combinePredicateReduction()
44497   EVT ExtractVT = Extract->getValueType(0);  in combineVPDPBUSDPattern()  local
44500   if (ExtractVT != MVT::i32)  in combineVPDPBUSDPattern()
44556       EVT::getVectorVT(*DAG.getContext(), ExtractVT,  in combineVPDPBUSDPattern()
44557                        DpVT.getSizeInBits() / ExtractVT.getSizeInBits());  in combineVPDPBUSDPattern()
44559   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtractVT, DP,  in combineVPDPBUSDPattern()
44569   EVT ExtractVT = Extract->getValueType(0);  in combineBasicSADPattern()  local
44572   if (ExtractVT != MVT::i32 && ExtractVT != MVT::i64)  in combineBasicSADPattern()
44628   unsigned ExtractSizeInBits = ExtractVT.getSizeInBits();  in combineBasicSADPattern()
44630   EVT ResVT = EVT::getVectorVT(*DAG.getContext(), ExtractVT,  in combineBasicSADPattern()
44633   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtractVT, SAD,  in combineBasicSADPattern()
44771     MVT ExtractVT = MVT::getVectorVT(SrcSVT.getSimpleVT(), 128 / SrcEltBits);  in combineExtractWithShuffle()  local
44772     return DAG.getNode(N->getOpcode(), dl, VT, DAG.getBitcast(ExtractVT, Src),  in combineExtractWithShuffle()
44846   EVT ExtractVT;  in combineExtractWithShuffle()  local
44849     ExtractVT = SrcVT;  in combineExtractWithShuffle()
44859     ExtractVT = EVT::getVectorVT(*DAG.getContext(), ExtractSVT, Mask.size());  in combineExtractWithShuffle()
44860     assert(SrcVT.getSizeInBits() == ExtractVT.getSizeInBits() &&  in combineExtractWithShuffle()
44874   if (SDValue V = GetLegalExtract(SrcOp, ExtractVT, ExtractIdx))  in combineExtractWithShuffle()
44877   if (N->getOpcode() == ISD::EXTRACT_VECTOR_ELT && ExtractVT == SrcVT)  in combineExtractWithShuffle()