| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 62 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
63 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
70 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
74 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | |
| H A D | X86FastISel.cpp | 1097 Register ExtReg = createResultReg(&X86::GR64RegClass); in X86SelectCallAddress() local
1099 TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) in X86SelectCallAddress()
1103 Reg = ExtReg; in X86SelectCallAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 111 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
112 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
119 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
123 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCCallLowering.cpp | 51 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
52 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 127 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
128 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
135 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
138 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 65 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
73 LLT Ty = MRI.getType(ExtReg); in assignValueToReg()
80 ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0); in assignValueToReg()
82 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
87 {MRI.getType(ExtReg)}) in assignValueToReg()
88 .addReg(ExtReg); in assignValueToReg()
89 ExtReg = ToSGPR.getReg(0); in assignValueToReg()
92 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| H A D | AMDGPUInstructionSelector.cpp | 2696 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); in selectG_SZA_EXT() local
2701 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) in selectG_SZA_EXT()
2708 .addReg(ExtReg) in selectG_SZA_EXT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 223 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
224 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
254 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
255 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 91 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
92 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
97 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
98 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 919 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
920 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
922 SrcReg1 = ExtReg; in PPCEmitCmp()
925 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
926 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
928 SrcReg2 = ExtReg; in PPCEmitCmp()
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| H A D | PPCISelLowering.cpp | 12952 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary() local
12954 ExtReg).addReg(dest); in EmitAtomicBinary()
12955 BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ExtReg).addReg(incr); in EmitAtomicBinary()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 7552 Register ExtReg = moveScalarRegClass(OffsetInst->getOperand(1).getReg(), in selectAddrModeWRO() local
7558 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
7849 Register ExtReg; in selectArithExtendedRegister() local
7876 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
7882 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
7888 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) { in selectArithExtendedRegister()
7889 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg); in selectArithExtendedRegister()
7898 ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB); in selectArithExtendedRegister()
7900 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectArithExtendedRegister()
7923 Register ExtReg = Extract->MI->getOperand(2).getReg(); in selectExtractHigh() local
[all …]
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| H A D | AArch64CallLowering.cpp | 297 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
298 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| H A D | AArch64LegalizerInfo.cpp | 1764 Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy}, in legalizeIntrinsic() local
1769 MIB.buildTrunc(DstReg, ExtReg); in legalizeIntrinsic()
1771 MIB.buildCopy(DstReg, ExtReg); in legalizeIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVInstructionSelector.cpp | 3471 Register ExtReg = MRI->createVirtualRegister(GR.getRegClass(ResType)); in selectFirstBitSet16() local
3472 bool Result = selectOpWithSrcs(ExtReg, ResType, I, {I.getOperand(2).getReg()}, in selectFirstBitSet16()
3476 selectFirstBitSet32(ResVReg, ResType, I, ExtReg, BitSetOpcode); in selectFirstBitSet16()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 3047 Register ExtReg = MRI.createGenericVirtualRegister(WideTy); in widenScalar() local
3049 MI.getOperand(0).setReg(ExtReg); in widenScalar()
3064 MIRBuilder.buildSMin(WideTy, ExtReg, MaxVal).getReg(0); in widenScalar()
3073 NewDst = MIRBuilder.buildUMin(WideTy, ExtReg, MaxVal).getReg(0); in widenScalar()
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