| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/ |
| H A D | M68kCallLowering.cpp | 62 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
63 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
70 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
74 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 66 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
74 LLT Ty = MRI.getType(ExtReg); in assignValueToReg()
81 ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0); in assignValueToReg()
83 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
88 {MRI.getType(ExtReg)}) in assignValueToReg()
89 .addReg(ExtReg); in assignValueToReg()
90 ExtReg = ToSGPR.getReg(0); in assignValueToReg()
93 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
236 Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); in assignValueToReg() local
237 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| H A D | AMDGPUInstructionSelector.cpp | 2452 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass); in selectG_SZA_EXT() local
2457 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg) in selectG_SZA_EXT()
2464 .addReg(ExtReg) in selectG_SZA_EXT()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | |
| H A D | X86FastISel.cpp | 1098 Register ExtReg = createResultReg(&X86::GR64RegClass); in X86SelectCallAddress() local
1100 TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) in X86SelectCallAddress()
1104 Reg = ExtReg; in X86SelectCallAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 112 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
113 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
120 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
124 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCCallLowering.cpp | 54 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
55 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 127 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
128 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
135 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
138 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 223 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg()
224 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
254 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
255 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
222 Register ExtReg = extendRegister(ValVReg, VA); assignValueToReg() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 99 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToAddress() local
100 MIRBuilder.buildStore(ExtReg, Addr, *MMO); in assignValueToAddress()
114 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
115 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 931 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
934 SrcReg1 = ExtReg; in PPCEmitCmp()
937 Register ExtReg = createResultReg(&PPC::GPRCRegClass); in PPCEmitCmp() local
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
940 SrcReg2 = ExtReg; in PPCEmitCmp()
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| H A D | PPCISelLowering.cpp | 12124 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); in EmitAtomicBinary() local
12126 ExtReg).addReg(dest); in EmitAtomicBinary()
12127 BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ExtReg).addReg(incr); in EmitAtomicBinary()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 7379 Register ExtReg = moveScalarRegClass(OffsetInst->getOperand(1).getReg(), in selectAddrModeWRO() local
7385 [=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectAddrModeWRO()
7671 Register ExtReg; in selectArithExtendedRegister() local
7698 ExtReg = ExtDef->getOperand(1).getReg(); in selectArithExtendedRegister()
7704 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()
7710 if (Ext == AArch64_AM::UXTW && MRI.getType(ExtReg).getSizeInBits() == 32) { in selectArithExtendedRegister()
7711 MachineInstr *ExtInst = MRI.getVRegDef(ExtReg); in selectArithExtendedRegister()
7720 ExtReg = moveScalarRegClass(ExtReg, AArch64::GPR32RegClass, MIB); in selectArithExtendedRegister()
7722 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }, in selectArithExtendedRegister()
7745 Register ExtReg = Extract->MI->getOperand(2).getReg(); in selectExtractHigh() local
[all …]
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| H A D | AArch64CallLowering.cpp | 295 Register ExtReg = extendRegister(ValVReg, VA); in assignValueToReg() local
296 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
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| H A D | AArch64LegalizerInfo.cpp | 1638 Register ExtReg = MIB.buildInstr(AArch64::G_EXTRACT_VECTOR_ELT, {ExtTy}, in legalizeIntrinsic() local
1643 MIB.buildTrunc(DstReg, ExtReg); in legalizeIntrinsic()
1645 MIB.buildCopy(DstReg, ExtReg); in legalizeIntrinsic()
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