| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVExtract.cpp | 52 unsigned genElemLoad(MachineInstr *ExtI, unsigned BaseR,
62 unsigned HexagonVExtract::genElemLoad(MachineInstr *ExtI, unsigned BaseR, in genElemLoad() argument
64 MachineBasicBlock &ExtB = *ExtI->getParent(); in genElemLoad()
65 DebugLoc DL = ExtI->getDebugLoc(); in genElemLoad()
68 Register ExtIdxR = ExtI->getOperand(2).getReg(); in genElemLoad()
69 unsigned ExtIdxS = ExtI->getOperand(2).getSubReg(); in genElemLoad()
78 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L2_loadri_io), ElemR) in genElemLoad()
86 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::A2_andir), IdxR) in genElemLoad()
87 .add(ExtI->getOperand(2)) in genElemLoad()
89 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L4_loadri_rr), ElemR) in genElemLoad()
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| H A D | HexagonConstExtenders.cpp | 390 void calculatePlacement(const ExtenderInit &ExtI, const IndexList &Refs,
392 Register insertInitializer(Loc DefL, const ExtenderInit &ExtI);
394 bool replaceInstrExpr(const ExtDesc &ED, const ExtenderInit &ExtI,
396 bool replaceInstr(unsigned Idx, Register ExtR, const ExtenderInit &ExtI);
467 : ExtI(EI), HRI(I) {} in PrintInit()
468 const HCE::ExtenderInit &ExtI; member
474 OS << '[' << P.ExtI.first << ", " in operator <<()
475 << PrintExpr(P.ExtI.second, P.HRI) << ']'; in operator <<()
1462 void HCE::calculatePlacement(const ExtenderInit &ExtI, const IndexList &Refs, in calculatePlacement() argument
1489 Register Rs = ExtI.second.Rs; // Only one reg allowed now. in calculatePlacement()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3429 MachineInstr *ExtI; in select() local
3496 ExtI = MIB.buildInstr(IsSigned ? AArch64::SBFMXri : AArch64::UBFMXri, in select()
3501 ExtI = MIB.buildInstr(IsSigned ? AArch64::SBFMWri : AArch64::UBFMWri, in select()
3509 constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); in select()
5358 MachineInstr *ExtI = nullptr; in selectUSMovFromExtend() local
5362 ExtI = MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {}) in selectUSMovFromExtend()
5368 ExtI = MIB.buildInstr(Opcode, {DefReg}, {Src0}).addImm(Lane); in selectUSMovFromExtend()
5370 constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); in selectUSMovFromExtend()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 7071 Instruction *ExtI; in foldICmpUsingBoolRange() local
7073 m_CombineAnd(m_Instruction(ExtI), in foldICmpUsingBoolRange()
7077 bool IsSExt = ExtI->getOpcode() == Instruction::SExt; in foldICmpUsingBoolRange()
7078 bool HasOneUse = ExtI->hasOneUse() && ExtI->getOperand(0)->hasOneUse(); in foldICmpUsingBoolRange()
7845 Instruction *ExtI; in visitICmpInst() local
7848 m_CombineAnd(m_Instruction(ExtI), m_ZExtOrSExt(m_Value(Y)))) && in visitICmpInst()
7856 unsigned ExtOpc = ExtI->getOpcode(); in visitICmpInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2633 MachineInstr *ExtI = in selectG_SZA_EXT() local
2638 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); in selectG_SZA_EXT()
2642 MachineInstr *ExtI = in selectG_SZA_EXT() local
2648 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); in selectG_SZA_EXT()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 7894 const auto ExtI = ExternallyUsedValues.find(Scalar); in buildExternalUses() local
7895 if (ExtI != ExternallyUsedValues.end()) { in buildExternalUses()
|