| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 97 ExtractElementInst *Ext1,
99 bool isExtractExtractCheap(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
103 void foldExtExtCmp(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
105 void foldExtExtBinop(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
351 ExtractElementInst *Ext0, ExtractElementInst *Ext1, in getShuffleExtract() argument
354 auto *Index1C = dyn_cast<ConstantInt>(Ext1->getIndexOperand()); in getShuffleExtract()
366 assert(VecTy == Ext1->getVectorOperand()->getType() && "Need matching types"); in getShuffleExtract()
370 TTI.getVectorInstrCost(*Ext1, VecTy, CostKind, Index1); in getShuffleExtract()
382 return Ext1; in getShuffleExtract()
387 return Ext1; in getShuffleExtract()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ |
| H A D | MsgPack.def | 94 HANDLE_MP_FIX_LEN(0x01, Ext1)
|
| /freebsd/contrib/llvm-project/llvm/lib/BinaryFormat/ |
| H A D | MsgPackWriter.cpp | 179 case FixLen::Ext1: in writeExt()
|
| H A D | MsgPackReader.cpp | 123 return createExt(Obj, FixLen::Ext1); in read()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9403 SDValue Ext1 = Ext.getValue(1); in LowerVectorExtend() local
9407 Ext1 = DAG.getNode(N->getOpcode(), DL, MVT::v8i32, Ext1); in LowerVectorExtend()
9410 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, Ext, Ext1); in LowerVectorExtend()
10333 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10339 SDValue Res0 = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
10345 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
10347 Res = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
13376 SDValue Ext1 = Mul.getOperand(1); in PerformVQDMULHCombine() local
13378 Ext1.getOpcode() != ISD::SIGN_EXTEND) in PerformVQDMULHCombine()
13383 if (Ext1.getOperand(0).getValueType() != VecVT || in PerformVQDMULHCombine()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15938 static bool areExtractExts(Value *Ext1, Value *Ext2) { in areExtractExts() argument
15944 if (!match(Ext1, m_ZExtOrSExt(m_Value())) || in areExtractExts()
15946 !areExtDoubled(cast<Instruction>(Ext1)) || in areExtractExts()
16158 auto Ext1 = cast<Instruction>(I->getOperand(0)); in shouldSinkOperands() local
16160 if (areExtractShuffleVectors(Ext1->getOperand(0), Ext2->getOperand(0))) { in shouldSinkOperands()
16161 Ops.push_back(&Ext1->getOperandUse(0)); in shouldSinkOperands()
17842 SDValue Ext1 = Op1.getOperand(0); in performUADDVAddCombine() local
17844 Ext1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in performUADDVAddCombine()
17845 Ext0.getOperand(0) != Ext1.getOperand(0)) in performUADDVAddCombine()
17853 Ext1.getConstantOperandVal(1) != VT.getVectorNumElements()) && in performUADDVAddCombine()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 3027 Instruction *Ext0, *Ext1; in foldICmpAddConstant() local
3031 m_CombineAnd(m_Instruction(Ext1), in foldICmpAddConstant()
3042 Res += isa<ZExtInst>(Ext1) ? 1 : -1; in foldICmpAddConstant()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 15086 SDValue Ext1 = FirstInput.getOperand(0); in DAGCombineBuildVector() local
15088 if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in DAGCombineBuildVector()
15092 ConstantSDNode *Ext1Op = dyn_cast<ConstantSDNode>(Ext1.getOperand(1)); in DAGCombineBuildVector()
15096 if (Ext1.getOperand(0).getValueType() != MVT::v4i32 || in DAGCombineBuildVector()
15097 Ext1.getOperand(0) != Ext2.getOperand(0)) in DAGCombineBuildVector()
15110 SDValue SrcVec = Ext1.getOperand(0); in DAGCombineBuildVector()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 3751 auto Ext1 = B.buildFPExt(F32, Src1, Flags); in legalizeFPow() local
3754 .addUse(Ext1.getReg(0)) in legalizeFPow()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 12856 SDValue Ext1 = DAG.getNode(Opcode, DL, VT, Op1); in tryToFoldExtendSelectLoad() local
12858 return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2); in tryToFoldExtendSelectLoad()
13524 SDValue Ext1 = DAG.getNode(ExtOpcode, DL, VT, N01); in foldSextSetcc() local
13525 return DAG.getSetCC(DL, VT, Ext0, Ext1, CC); in foldSextSetcc()
22384 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op1, Index); in scalarizeExtractedBinop() local
22385 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 44911 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, in scalarizeExtEltFP() local
44913 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2)); in scalarizeExtEltFP()
44935 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in scalarizeExtEltFP() local
44939 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2); in scalarizeExtEltFP()
57156 SDValue Ext1 = extractSubVector(InVec.getOperand(1), 0, DAG, DL, 128); in combineEXTRACT_SUBVECTOR() local
57158 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, Ext2); in combineEXTRACT_SUBVECTOR()
57174 SDValue Ext1 = in combineEXTRACT_SUBVECTOR() local
57177 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, InVec.getOperand(2)); in combineEXTRACT_SUBVECTOR()
57178 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1); in combineEXTRACT_SUBVECTOR()
|