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Searched refs:Enc (Results 1 – 25 of 30) sorted by relevance

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/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DXCore.cpp103 std::string Enc; member in __anonc019d7680111::FieldEncoding
105 FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {} in FieldEncoding()
106 StringRef str() { return Enc; } in str()
109 return Enc < rhs.Enc; in operator <()
292 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
300 SmallStringEnc Enc; in emitTargetMD() local
301 if (getTypeString(Enc, D, CGM, TSC)) { in emitTargetMD()
304 llvm::MDString::get(Ctx, Enc.str())}; in emitTargetMD()
327 static bool appendType(SmallStringEnc &Enc, QualType QType,
339 SmallStringEnc Enc; in extractFieldType() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp309 auto Enc = getLit64Encoding(static_cast<uint64_t>(Imm), STI, true); in getLitEncoding() local
310 return (HasMandatoryLiteral && Enc == 255) ? 254 : Enc; in getLitEncoding()
443 auto Enc = getLitEncoding(Op, Desc.operands()[i], STI); in encodeInstruction() local
444 if (!Enc || (*Enc != 255 && *Enc != 254)) in encodeInstruction()
458 if (*Enc == 254) { in encodeInstruction()
517 auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI); in getSDWASrcEncoding() local
518 if (Enc && *Enc != 255) { in getSDWASrcEncoding()
519 Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK; in getSDWASrcEncoding()
549 unsigned Enc = MRI.getEncodingValue(Reg); in getAVOperandEncoding() local
550 unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK; in getAVOperandEncoding()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td17 class Wi<bits<16> Enc, string n> : Register<n> {
18 let HWEncoding = Enc;
24 class Ri<bits<16> Enc, string n, list<Register> subregs>
26 let HWEncoding = Enc;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td29 class MipsReg<bits<16> Enc, string n> : Register<n> {
30 let HWEncoding = Enc;
34 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
36 let HWEncoding = Enc;
41 class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
44 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
45 : MipsRegWithSubRegs<Enc, n, subregs> {
50 class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
53 class AFPR<bits<16> Enc, string n, list<Register> subregs>
54 : MipsRegWithSubRegs<Enc, n, subregs> {
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/freebsd/contrib/llvm-project/llvm/include/llvm/Bitstream/
H A DBitCodes.h49 uint64_t Enc : 3; // The encoding to use. in LLVM_PREFERRED_TYPE()
58 : Val(Data), IsLiteral(false), Enc(E) {} in Val()
67 Encoding getEncoding() const { assert(isEncoding()); return (Encoding)Enc; } in getEncoding()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td13 class SparcReg<bits<16> Enc, string n> : Register<n> {
14 let HWEncoding = Enc;
18 class SparcCtrlReg<bits<16> Enc, string n,
20 let HWEncoding = Enc;
38 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>;
41 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
47 class Rf<bits<16> Enc, string n> : SparcReg<Enc,
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td14 class LoongArchReg<bits<16> Enc, string n, list<string> alt = []>
16 let HWEncoding = Enc;
20 class LoongArchRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs,
23 let HWEncoding = Enc;
27 class LoongArchReg32<bits<16> Enc, string n, list<string> alt = []>
29 let HWEncoding = Enc;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp172 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm()); in LowerARMMachineInstrToMCInst() local
173 if (Enc != -1) in LowerARMMachineInstrToMCInst()
174 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
H A DARMRegisterInfo.td16 class ARMReg<bits<16> Enc, string n, list<Register> subregs = [],
18 let HWEncoding = Enc;
25 class ARMFReg<bits<16> Enc, string n> : Register<n> {
26 let HWEncoding = Enc;
H A DARMInstrVFP.td66 uint32_t Enc = ARM_AM::getFP16Imm(N->getValueAPF());
67 return CurDAG->getTargetConstant(Enc, SDLoc(N), MVT::i32);
74 uint32_t Enc = ARM_AM::getFP32FP16Imm(N->getValueAPF());
75 return CurDAG->getTargetConstant(Enc, SDLoc(N), MVT::i32);
83 uint32_t Enc = ARM_AM::getFP32Imm(N->getValueAPF());
84 return CurDAG->getTargetConstant(Enc, SDLoc(N), MVT::i32);
105 uint32_t Enc = ARM_AM::getFP64Imm(N->getValueAPF());
106 return CurDAG->getTargetConstant(Enc, SDLoc(N), MVT::i32);
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td14 class CSKYReg<bits<6> Enc, string n, list<string> alt = []> : Register<n> {
15 let HWEncoding{5 - 0} = Enc;
19 class CSKYFReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
20 let HWEncoding{4 - 0} = Enc;
/freebsd/crypto/openssl/doc/man3/
H A DSSL_CIPHER_get_name.pod141 =item Enc=<symmetric encryption method>
153 ECDHE-RSA-AES256-GCM-SHA256 TLSv1.2 Kx=ECDH Au=RSA Enc=AESGCM(256) Mac=AEAD
154 RSA-PSK-AES256-CBC-SHA384 TLSv1.0 Kx=RSAPSK Au=RSA Enc=AES(256) Mac=SHA384
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/IPO/
H A DAttributor.h614 IRPosition() : Enc(nullptr, ENC_VALUE) { verify(); }
700 return Enc == RHS.Enc && RHS.CBContext == CBContext;
952 operator void *() const { return Enc.getOpaqueValue(); }
958 Enc.setFromOpaqueValue(Ptr);
972 Enc = {&AnchorVal, ENC_FLOATING_FUNCTION};
974 Enc = {&AnchorVal, ENC_VALUE};
978 Enc = {&AnchorVal, ENC_VALUE};
982 Enc = {&AnchorVal, ENC_RETURNED_VALUE};
985 Enc = {&AnchorVal, ENC_VALUE};
1020 Enc = {&U, ENC_CALL_SITE_ARGUMENT_USE};
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td14 class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
15 let HWEncoding{4-0} = Enc;
19 class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
22 let HWEncoding{4-0} = Enc;
26 class RISCVReg16<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
27 let HWEncoding{4-0} = Enc;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DAccelTable.cpp423 for (const DebugNamesAbbrev::AttributeEncoding &Enc : AttrVect) { in Profile() local
424 ID.AddInteger(Enc.Index); in Profile()
425 ID.AddInteger(Enc.Form); in Profile()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DX86FoldTablesEmitter.cpp487 uint8_t Enc = byteFromBitsInit(RegRec->getValueAsBitsInit("OpEncBits")); in addEntryWithFlags() local
492 } else if (!Enc && !isExplicitUnalign(RegInst) && in addEntryWithFlags()
H A DDecoderEmitter.cpp1841 const EncodingAndInst &Enc = AllInstructions[Opcode.EncodingID]; in emitTableEntries() local
1842 errs() << '\t' << Enc << ' '; in emitTableEntries()
1843 dumpBits(errs(), getBitsField(*Enc.EncodingDef, "Inst")); in emitTableEntries()
H A DX86DisassemblerTables.cpp884 for (const auto &[Enc, Ty] : OperandList) { in emitInstructionInfo()
885 const char *Encoding = stringForOperandEncoding(Enc); in emitInstructionInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInsertWaitcnts.cpp1456 unsigned Enc = AMDGPU::encodeWaitcnt(IV, Wait); in createNewWaitcnt() local
1458 BuildMI(Block, It, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(Enc); in createNewWaitcnt()
1707 unsigned Enc = AMDGPU::encodeLoadcntDscnt(IV, Wait); in createNewWaitcnt() local
1710 .addImm(Enc); in createNewWaitcnt()
1715 unsigned Enc = AMDGPU::encodeStorecntDscnt(IV, Wait); in createNewWaitcnt() local
1719 .addImm(Enc); in createNewWaitcnt()
/freebsd/contrib/llvm-project/llvm/include/llvm/Demangle/
H A DItaniumDemangle.h2997 char Enc[2]; // Encoding member
3006 : Enc{E[0], E[1]}, Kind{K}, Flag{F}, Prec{P}, Name{N} {} in OperatorInfo()
3010 return *this < Other.Enc;
3013 return Enc[0] < Peek[0] || (Enc[0] == Peek[0] && Enc[1] < Peek[1]);
3016 return Enc[0] == Peek[0] && Enc[1] == Peek[1];
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7053 uint64_t Enc = (32 - *MaybeImmed) & 0x1f; in selectShiftA_32() local
7054 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_32()
7062 uint64_t Enc = 31 - *MaybeImmed; in selectShiftB_32() local
7063 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_32()
7071 uint64_t Enc = (64 - *MaybeImmed) & 0x3f; in selectShiftA_64() local
7072 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftA_64()
7080 uint64_t Enc = 63 - *MaybeImmed; in selectShiftB_64() local
7081 return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(Enc); }}}; in selectShiftB_64()
7958 uint64_t Enc = AArch64_AM::encodeLogicalImmediate(CstVal, 32); in renderLogicalImm32() local
7959 MIB.addImm(Enc); in renderLogicalImm32()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2681 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); in addModImmNotOperands() local
2682 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNotOperands()
2688 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); in addModImmNegOperands() local
2689 Inst.addOperand(MCOperand::createImm(Enc)); in addModImmNegOperands()
4602 unsigned Enc, MCRegister Reg) { in insertNoDuplicates() argument
4603 Regs.emplace_back(Enc, Reg); in insertNoDuplicates()
4605 if (J->first == Enc) { in insertNoDuplicates()
4609 if (J->first < Enc) in insertNoDuplicates()
5569 int Enc = ARM_AM::getSOImmVal(Imm1); in parseModImm() local
5570 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { in parseModImm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp1802 unsigned Enc = 0; in getDefaultCustomOperandEncoding() local
1806 Enc |= Op.encode(Op.Default); in getDefaultCustomOperandEncoding()
1808 return Enc; in getDefaultCustomOperandEncoding()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td48 class SPE<string n, bits<5> Enc, list<Register> subregs = []> : PPCReg<n> {
49 let HWEncoding{4-0} = Enc;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td15 class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
17 let HWEncoding = Enc;

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