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Searched refs:EltSize (Results 1 – 25 of 83) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCLegalizerInfo.cpp31 const int EltSize = QueryTy.getElementType().getSizeInBits(); in isRegisterType() local
32 return (EltSize == 8 || EltSize == 16 || EltSize == 32 || EltSize == 64); in isRegisterType()
/freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/
H A DCBufferDataLayout.cpp81 TypeSize EltSize = getTypeAllocSize(AT->getElementType()); in getTypeAllocSize() local
82 TypeSize AlignedEltSize = alignTo4Dwords(EltSize); in getTypeAllocSize()
84 return TypeSize::getFixed(AlignedEltSize * (NumElts - 1) + EltSize); in getTypeAllocSize()
102 TypeSize EltSize = getTypeAllocSize(EltTy); in getStructLayout() local
107 Offset = Offset.getWithIncrement(EltSize); in getStructLayout()
H A DDXILCBufferAccess.cpp29 unsigned int EltSize; member
39 EltSize = 2; in CBufferRowIntrin()
45 EltSize = 4; in CBufferRowIntrin()
51 EltSize = 8; in CBufferRowIntrin()
132 (TargetOffset % hlsl::CBufferRowSizeInBytes) / Intrin.EltSize; in loadValue()
143 ((DL.getTypeSizeInBits(Ty) / 8) / Intrin.EltSize) - 1; in loadValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ShuffleDecode.cpp400 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, in DecodeEXTRQIMask() argument
410 if (0 != (Len % EltSize) || 0 != (Idx % EltSize)) in DecodeEXTRQIMask()
424 Len /= EltSize; in DecodeEXTRQIMask()
425 Idx /= EltSize; in DecodeEXTRQIMask()
437 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx, in DecodeINSERTQIMask() argument
447 if (0 != (Len % EltSize) || 0 != (Idx % EltSize)) in DecodeINSERTQIMask()
461 Len /= EltSize; in DecodeINSERTQIMask()
462 Idx /= EltSize; in DecodeINSERTQIMask()
H A DX86ShuffleDecode.h141 void DecodeEXTRQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
145 void DecodeINSERTQIMask(unsigned NumElts, unsigned EltSize, int Len, int Idx,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PerfectShuffle.h6703 inline bool isREVMask(ArrayRef<int> M, unsigned EltSize, unsigned NumElts, in isREVMask() argument
6712 BlockElts = BlockSize / EltSize; in isREVMask()
6714 if (BlockSize <= EltSize || BlockSize != BlockElts * EltSize) in isREVMask()
H A DAArch64TargetTransformInfo.h366 unsigned EltSize = DataTypeTy->getElementType()->getScalarSizeInBits(); in isLegalNTStoreLoad() local
367 return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 && in isLegalNTStoreLoad()
368 EltSize <= 128 && isPowerOf2_64(EltSize); in isLegalNTStoreLoad()
H A DAArch64RegisterInfo.td1870 class MatrixTileAsmOperand<string RC, int EltSize> : AsmOperandClass {
1871 let Name = "MatrixTile" # EltSize;
1877 # EltSize # ", AArch64::" # RC # "RegClassID>";
1880 class MatrixTileOperand<int EltSize, int NumBitsForTile, RegisterClass RC>
1882 let ParserMatchClass = MatrixTileAsmOperand<!cast<string>(RC), EltSize>;
1895 class MatrixTileVectorAsmOperand<string RC, int EltSize, int IsVertical>
1897 let Name = "MatrixTileVector" # !if(IsVertical, "V", "H") # EltSize;
1904 # EltSize # ", AArch64::" # RC # "RegClassID>";
1907 class MatrixTileVectorOperand<int EltSize, int NumBitsForTile,
1910 let ParserMatchClass = MatrixTileVectorAsmOperand<!cast<string>(RC), EltSize,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILoadStoreOptimizer.cpp111 unsigned EltSize; member
237 unsigned read2Opcode(unsigned EltSize) const;
238 unsigned read2ST64Opcode(unsigned EltSize) const;
243 unsigned write2Opcode(unsigned EltSize) const;
244 unsigned write2ST64Opcode(unsigned EltSize) const;
814 EltSize = in setMI()
819 EltSize = in setMI()
826 EltSize = AMDGPU::convertSMRDOffsetUnits(*LSO.STM, 4); in setMI()
829 EltSize = 4; in setMI()
1044 if ((CI.Offset % CI.EltSize != 0) || (Paired.Offset % CI.EltSize != 0)) in offsetsCanBeCombined()
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H A DR600TargetTransformInfo.cpp119 unsigned EltSize = in getVectorInstrCost() local
121 if (EltSize < 32) { in getVectorInstrCost()
H A DSIRegisterInfo.cpp105 unsigned EltSize = 4; member
132 SplitParts = TRI.getRegSplitParts(RC, EltSize); in SGPRSpillBuilder()
1530 unsigned EltSize) { in getFlatScratchSpillOpcode() argument
1540 switch (EltSize) { in getFlatScratchSpillOpcode()
1598 unsigned EltSize = IsBlock ? RegWidth in buildSpillLoadStore() local
1601 unsigned NumSubRegs = RegWidth / EltSize; in buildSpillLoadStore()
1602 unsigned Size = NumSubRegs * EltSize; in buildSpillLoadStore()
1608 int64_t MaxOffset = Offset + Size + RemSize - EltSize; in buildSpillLoadStore()
1611 if (IsFlat && EltSize > 4) { in buildSpillLoadStore()
1612 LoadStoreOp = getFlatScratchSpillOpcode(TII, LoadStoreOp, EltSize); in buildSpillLoadStore()
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H A DAMDGPULegalizerInfo.cpp79 const unsigned EltSize = EltTy.getSizeInBits(); in isSmallOddVector() local
81 EltSize > 1 && EltSize < 32 && in isSmallOddVector()
130 const int EltSize = EltTy.getSizeInBits(); in moreEltsToNext32Bit() local
133 assert(EltSize < 32); in moreEltsToNext32Bit()
135 const int NewNumElts = (32 * NextMul32 + EltSize - 1) / EltSize; in moreEltsToNext32Bit()
145 const unsigned EltSize = Ty.getElementType().getSizeInBits(); in moreElementsToNextExistingRegClass() local
146 const unsigned MaxNumElts = MaxRegisterSize / EltSize; in moreElementsToNextExistingRegClass()
148 assert(EltSize == 32 || EltSize == 64); in moreElementsToNextExistingRegClass()
154 if (SIRegisterInfo::getSGPRClassForBitWidth(NewNumElts * EltSize)) in moreElementsToNextExistingRegClass()
232 const int EltSize = EltTy.getSizeInBits(); in isRegisterVectorElementType() local
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/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuilder.h249 CharUnits EltSize = variable
256 Addr.getAlignment().alignmentAtOffset(Index * EltSize),
269 CharUnits EltSize = CharUnits::fromQuantity(DL.getTypeAllocSize(ElTy)); variable
273 ElTy, Addr.getAlignment().alignmentAtOffset(Index * EltSize),
286 CharUnits EltSize = CharUnits::fromQuantity(DL.getTypeAllocSize(ElTy)); variable
290 Addr.getAlignment().alignmentAtOffset(Index * EltSize));
299 CharUnits EltSize = variable
305 Addr.getAlignment().alignmentOfArrayElement(EltSize));
/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A DPPC.cpp18 CharUnits EltSize, const ComplexType *CTy) { in complexTempStructure() argument
27 CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize - EltSize); in complexTempStructure()
29 2 * SlotSize - EltSize); in complexTempStructure()
259 CharUnits EltSize = TypeInfo.Width / 2; in EmitVAArg() local
260 if (EltSize < SlotSize) in EmitVAArg()
261 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy); in EmitVAArg()
983 CharUnits EltSize = TypeInfo.Width / 2; in EmitVAArg() local
984 if (EltSize < SlotSize) in EmitVAArg()
985 return complexTempStructure(CGF, VAListAddr, Ty, SlotSize, EltSize, CTy); in EmitVAArg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp160 unsigned EltSize = Ty.getScalarSizeInBits(); in matchREV() local
163 if (EltSize == 64) in matchREV()
170 if (isREVMask(ShuffleMask, EltSize, NumElts, LaneSize)) { in matchREV()
459 auto EltSize = Builder.buildConstant(IdxTy, EltTy.getSizeInBytes()); in applyNonConstInsert() local
460 Register Mul = Builder.buildMul(IdxTy, And, EltSize).getReg(0); in applyNonConstInsert()
982 unsigned EltSize = MRI.getType(LHS).getScalarSizeInBits(); in matchLowerVectorFCMP() local
983 if (EltSize == 16 && !ST.hasFullFP16()) in matchLowerVectorFCMP()
985 if (EltSize != 16 && EltSize != 32 && EltSize != 64) in matchLowerVectorFCMP()
H A DAArch64PostLegalizerCombiner.cpp451 unsigned EltSize = DstTy.getScalarSizeInBits(); in matchExtMulToMULL() local
458 return EltSize >= Ty.getScalarSizeInBits() * 2; in matchExtMulToMULL()
487 APInt Mask = APInt::getHighBitsSet(EltSize, EltSize / 2); in matchExtMulToMULL()
513 if (KB->computeNumSignBits(SExtOp) > EltSize / 2) { in matchExtMulToMULL()
520 KB->computeNumSignBits(MI.getOperand(1).getReg()) > EltSize / 2 && in matchExtMulToMULL()
521 KB->computeNumSignBits(MI.getOperand(2).getReg()) > EltSize / 2) { in matchExtMulToMULL()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1674 unsigned EltSize = VTy->getScalarSizeInBits(); in getGatherScatterOpCost() local
1695 if (EltSize < 8 || Alignment < EltSize / 8) in getGatherScatterOpCost()
1698 unsigned ExtSize = EltSize; in getGatherScatterOpCost()
1712 if (((TypeSize == 32 && (EltSize == 8 || EltSize == 16)) || in getGatherScatterOpCost()
1713 (TypeSize == 16 && EltSize == 8)) && in getGatherScatterOpCost()
1726 if (((EltSize == 16 && TypeSize == 32) || in getGatherScatterOpCost()
1727 (EltSize == 8 && (TypeSize == 32 || TypeSize == 16))) && in getGatherScatterOpCost()
1771 unsigned EltSize = ValVT.getScalarSizeInBits(); in getArithmeticReductionCost() local
1777 ((EltSize == 32 && ST->hasVFP2Base()) || in getArithmeticReductionCost()
1778 (EltSize == 64 && ST->hasFP64()) || in getArithmeticReductionCost()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h941 unsigned NumElts, unsigned EltSize, in isSequenceFromUnmerge() argument
947 MI.getSourceReg(i), EltSize, EltUnmergeIdx); in isSequenceFromUnmerge()
967 unsigned EltSize = EltTy.getSizeInBits(); in tryCombineMergeLike() local
971 auto *Unmerge = findUnmergeThatDefinesReg(Elt0, EltSize, Elt0UnmergeIdx); in tryCombineMergeLike()
989 if (!isSequenceFromUnmerge(MI, 0, Unmerge, 0, NumMIElts, EltSize, in tryCombineMergeLike()
1015 EltSize, false)) in tryCombineMergeLike()
1019 unsigned DstIdx = (Elt0UnmergeIdx * EltSize) / DstTy.getSizeInBits(); in tryCombineMergeLike()
1043 EltSize, EltUnmergeIdx); in tryCombineMergeLike()
1048 if (!isSequenceFromUnmerge(MI, i, UnmergeI, 0, NumElts, EltSize, in tryCombineMergeLike()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4659 unsigned EltSize = MemIntr->getMemoryVT().getSizeInBits(); in matchVPTERNLOG() local
4660 assert((EltSize == 32 || EltSize == 64) && "Unexpected broadcast size!"); in matchVPTERNLOG()
4662 bool UseD = EltSize == 32; in matchVPTERNLOG()
6508 unsigned EltSize = ValueSVT.getSizeInBits(); in Select() local
6513 if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 32) in Select()
6515 else if (IndexVT == MVT::v8i32 && NumElts == 8 && EltSize == 32) in Select()
6517 else if (IndexVT == MVT::v16i32 && NumElts == 16 && EltSize == 32) in Select()
6519 else if (IndexVT == MVT::v4i32 && NumElts == 2 && EltSize == 64) in Select()
6521 else if (IndexVT == MVT::v4i32 && NumElts == 4 && EltSize == 64) in Select()
6523 else if (IndexVT == MVT::v8i32 && NumElts == 8 && EltSize == 64) in Select()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp108 TypeSize EltSize = DL.getTypeAllocSize(EltTy); in ComputeValueVTs() local
111 StartingOffset + i * EltSize); in ComputeValueVTs()
161 uint64_t EltSize = DL.getTypeAllocSize(EltTy).getFixedValue(); in computeValueLLTs() local
164 StartingOffset + i * EltSize); in computeValueLLTs()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp702 unsigned EltSize = Val->getScalarSizeInBits(); in getVectorInstrCost() local
704 unsigned MaskCostForOneBitSize = (VecMaskCost && EltSize == 1) ? 1 : 0; in getVectorInstrCost()
719 unsigned EltSize = Val->getScalarSizeInBits(); in getVectorInstrCost() local
721 if (EltSize == 64 && Index != -1U) in getVectorInstrCost()
723 if (EltSize == 32) { in getVectorInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DLoads.cpp295 APInt EltSize(DL.getIndexTypeSizeInBits(Ptr->getType()), in isDereferenceableAndAlignedInLoop() local
302 Ptr, Alignment, EltSize, DL, &*L->getHeader()->getFirstNonPHIIt(), AC, in isDereferenceableAndAlignedInLoop()
320 if (EltSize.urem(Alignment.value()) != 0) in isDereferenceableAndAlignedInLoop()
324 if (EltSize.ugt(Step->getAPInt().abs())) in isDereferenceableAndAlignedInLoop()
/freebsd/contrib/llvm-project/clang/lib/AST/ByteCode/
H A DInterpBuiltinBitCast.cpp232 unsigned EltSize = in CheckBitcastType() local
235 if ((NElts * EltSize) % ASTCtx.getCharWidth() != 0) { in CheckBitcastType()
242 << QualType(VT, 0) << EltSize << NElts << ASTCtx.getCharWidth(); in CheckBitcastType()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DDerivedTypes.h567 unsigned EltSize = EltTy->getScalarSizeInBits(); in getWithSizeAndScalar() local
568 if (!SizeTy->getPrimitiveSizeInBits().isKnownMultipleOf(EltSize)) in getWithSizeAndScalar()
573 .divideCoefficientBy(EltSize); in getWithSizeAndScalar()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h194 template <int EltSize>
220 template <int EltSize>

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