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Searched refs:EXTRACT_SUBVECTOR (Results 1 – 25 of 29) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp59 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
1085 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1586 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
1589 ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_INSERT_SUBVECTOR()
3141 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; in SplitVectorOperand()
3497 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); in SplitVecOp_EXTRACT_SUBVECTOR()
3500 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
4325 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; in WidenVectorResult()
4801 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, in WidenVecRes_BinaryCanTrap()
4803 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, d in WidenVecRes_BinaryCanTrap()
[all...]
H A DDAGCombiner.cpp729 case ISD::EXTRACT_SUBVECTOR: in getStoreSource()
1958 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
7187 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C && in visitAND()
7201 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ZeroExtExtendee, in visitAND()
14848 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && in visitSIGN_EXTEND_INREG()
14859 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), VT, SignExtExtendee, in visitSIGN_EXTEND_INREG()
15186 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
15193 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT, in visitTRUNCATE()
20274 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
20283 unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR in mergeStoresOfConstantsOrVecElts()
[all …]
H A DLegalizeIntegerTypes.cpp122 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
552 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
1693 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx); in PromoteIntRes_TRUNCATE()
1970 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; in PromoteIntegerOperand()
5746 SDValue Step1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NInVT, InOp0, in PromoteIntRes_EXTRACT_SUBVECTOR()
5750 ISD::EXTRACT_SUBVECTOR, dl, OutVT, Step1, in PromoteIntRes_EXTRACT_SUBVECTOR()
5758 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), OutVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
5773 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
6106 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()
H A DSelectionDAGDumper.cpp328 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
H A DSelectionDAG.cpp2857 case ISD::EXTRACT_SUBVECTOR: { in isSplatValue()
3329 case ISD::EXTRACT_SUBVECTOR: { in computeKnownBits()
4924 case ISD::EXTRACT_SUBVECTOR: { in ComputeNumSignBits()
5823 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR || in foldCONCAT_VECTORS()
7254 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
7282 case ISD::EXTRACT_SUBVECTOR: { in getNode()
7542 if (N1.isUndef() && N2.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
11964 while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) in peekThroughExtractSubvectors()
12305 return getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Op), SubVT, Op, in matchBinOpReduction()
12360 if (Op0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
[all …]
H A DSelectionDAGBuilder.cpp434 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, PartEVT, Val, in getCopyFromPartsVector()
821 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, in getCopyToPartsVector()
4114 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result, in visitShuffleVector()
4159 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src, in visitShuffleVector()
8002 Subvectors.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ReducedTy, in visitIntrinsicCall()
8099 DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index)); in visitIntrinsicCall()
12434 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
12436 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h587 EXTRACT_SUBVECTOR, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1102 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in AArch64TargetLowering()
1503 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
1870 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForNEON()
2048 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Default); in addTypeForFixedLengthSVE()
5294 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && in LowerMUL()
5296 N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in LowerMUL()
5337 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OVT, in LowerMUL()
5348 ISD::EXTRACT_SUBVECTOR, DL, OVT, in LowerMUL()
5664 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v1i64, in LowerINTRINSIC_WO_CHAIN()
5676 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v1i64, in LowerINTRINSIC_WO_CHAIN()
[all …]
H A DAArch64ISelDAGToDAG.cpp164 if (N->getOpcode() != ISD::EXTRACT_SUBVECTOR || in SelectExtractHigh()
4450 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && "Invalid Node!"); in trySelectCastScalableToFixedLengthVector()
4633 case ISD::EXTRACT_SUBVECTOR: { in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h464 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in LoHalf()
475 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in HiHalf()
H A DHexagonISelLoweringHVX.cpp134 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
234 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
391 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
1600 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubTy, in extractSubvector()
3133 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RetTy, in WidenHvxSetCC()
3208 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG); in LowerHvxOperation()
3333 // expects, so insert EXTRACT_SUBVECTOR to bring it back to the in LegalizeHvxResize()
H A DHexagonISelDAGToDAG.cpp1022 case ISD::EXTRACT_SUBVECTOR: return SelectHvxExtractSubvector(N); in Select()
1038 case ISD::EXTRACT_SUBVECTOR: return SelectExtractSubvector(N); in Select()
H A DHexagonISelLowering.cpp1664 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1713 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3367 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp2809 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SingleTy, FoldedShuff, in ppHvxShuffleOfShuffle()
2816 if (V.getOpcode() != ISD::EXTRACT_SUBVECTOR) in ppHvxShuffleOfShuffle()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp254 case ISD::EXTRACT_SUBVECTOR: in getIdiomaticVectorType()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp753 ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR, in RISCVTargetLowering()
879 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1021 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1074 ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
1104 ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
1153 // We use EXTRACT_SUBVECTOR as a "cast" from scalable to fixed. in RISCVTargetLowering()
1154 setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT, in RISCVTargetLowering()
1304 ISD::EXTRACT_SUBVECTOR}, in RISCVTargetLowering()
2294 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
2748 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, D in convertFromScalableVector()
[all...]
H A DRISCVISelDAGToDAG.cpp2234 case ISD::EXTRACT_SUBVECTOR: { in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp983 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1638 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1756 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2000 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
2149 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2270 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f16, Legal); in X86TargetLowering()
2308 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f16, Legal); in X86TargetLowering()
2513 ISD::EXTRACT_SUBVECTOR, in X86TargetLowering()
3122 if (UI->getOpcode() != ISD::EXTRACT_SUBVECTOR || !UI->hasOneUse() || in shouldReduceLoadWidth()
3197 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
[all …]
H A DX86ISelLowering.h1261 Op.getOpcode() == ISD::EXTRACT_SUBVECTOR || in isTargetCanonicalConstantNode()
H A DX86ISelDAGToDAG.cpp1083 SDValue Extract = CurDAG->getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp188 ISD::EXTRACT_SUBVECTOR}); in WebAssemblyTargetLowering()
2536 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performVectorExtendCombine()
2718 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, VecIdx); in extractSubVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp198 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
456 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addMVEVectorTypes()
6240 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
8300 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8306 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8311 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8314 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9786 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9788 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9790 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp333 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
632 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
1930 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
2019 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val, in convertArgType()
6252 Src0SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src0, in lowerLaneOp()
6256 Src1SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src1, in lowerLaneOp()
6260 Src2SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src2, in lowerLaneOp()
7410 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE()
7803 Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT, in constructRetValue()
8302 auto Subvector = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp, in lowerSBuffer()
[all …]
H A DAMDGPUISelLowering.cpp444 ISD::EXTRACT_SUBVECTOR, in AMDGPUTargetLowering()
1378 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
1759 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in splitVector()
1762 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL, in splitVector()
1855 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td802 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
810 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;

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