Home
last modified time | relevance | path

Searched refs:EXTRACT_SUBVECTOR (Results 1 – 25 of 33) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h601 EXTRACT_SUBVECTOR, enumerator
H A DSDPatternMatch.h935 return BinaryOpc_match<LHS, RHS>(ISD::EXTRACT_SUBVECTOR, Vec, Idx);
H A DSelectionDAG.h969 return getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Vec,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1144 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in AArch64TargetLowering()
1595 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in AArch64TargetLowering()
2039 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForNEON()
2284 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Default); in addTypeForFixedLengthSVE()
5445 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && in LowerMUL()
5447 N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in LowerMUL()
5488 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OVT, in LowerMUL()
5499 ISD::EXTRACT_SUBVECTOR, DL, OVT, in LowerMUL()
5900 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v1i64, in LowerINTRINSIC_WO_CHAIN()
5912 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v1i64, in LowerINTRINSIC_WO_CHAIN()
[all …]
H A DAArch64ISelDAGToDAG.cpp169 if (N->getOpcode() != ISD::EXTRACT_SUBVECTOR || in SelectExtractHigh()
4552 assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && "Invalid Node!"); in trySelectCastScalableToFixedLengthVector()
4862 case ISD::EXTRACT_SUBVECTOR: { in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h481 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in LoHalf()
492 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); in HiHalf()
H A DHexagonISelLoweringHVX.cpp136 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
238 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
401 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
1616 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubTy, in extractSubvector()
3170 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RetTy, in WidenHvxSetCC()
3245 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelDAGToDAG.cpp1023 case ISD::EXTRACT_SUBVECTOR: return SelectHvxExtractSubvector(N); in Select()
1039 case ISD::EXTRACT_SUBVECTOR: return SelectExtractSubvector(N); in Select()
H A DHexagonISelLowering.cpp1734 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1787 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3389 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp2800 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SingleTy, FoldedShuff, in ppHvxShuffleOfShuffle()
2807 if (V.getOpcode() != ISD::EXTRACT_SUBVECTOR) in ppHvxShuffleOfShuffle()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp254 case ISD::EXTRACT_SUBVECTOR: in getIdiomaticVectorType()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp996 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1662 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
1785 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2033 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
2212 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
2338 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f16, Legal); in X86TargetLowering()
2384 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f16, Legal); in X86TargetLowering()
2643 ISD::EXTRACT_SUBVECTOR, in X86TargetLowering()
3279 if (User->getOpcode() == ISD::EXTRACT_SUBVECTOR && in shouldReduceLoadWidth()
3373 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
[all …]
H A DX86ISelLowering.h1347 Op.getOpcode() == ISD::EXTRACT_SUBVECTOR || in isTargetCanonicalConstantNode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp59 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
1133 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1654 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
1657 ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
3280 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, Load, in SplitVecRes_VP_SPLICE()
3283 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, Load, in SplitVecRes_VP_SPLICE()
3413 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; in SplitVectorOperand()
3808 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); in SplitVecOp_EXTRACT_SUBVECTOR()
4685 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; in WidenVectorResult()
5403 ISD::EXTRACT_SUBVECTOR, DL, OtherVT, SDValue(WideNode, OtherNo), Zero); in WidenVecRes_OverflowOp()
[all …]
H A DDAGCombiner.cpp738 case ISD::EXTRACT_SUBVECTOR: in getStoreSource()
2021 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
7610 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C && in visitAND()
7624 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ZeroExtExtendee, in visitAND()
15753 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && in visitSIGN_EXTEND_INREG()
15764 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SignExtExtendee, in visitSIGN_EXTEND_INREG()
16236 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
16243 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT, in visitTRUNCATE()
21288 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
21297 unsigned OpC = MemVT.isVector() ? ISD::EXTRACT_SUBVECTOR in mergeStoresOfConstantsOrVecElts()
[all …]
H A DLegalizeIntegerTypes.cpp126 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
569 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
1738 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx); in PromoteIntRes_TRUNCATE()
2021 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; in PromoteIntegerOperand()
2227 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, Cast, in PromoteIntOp_BITCAST()
5989 SDValue Step1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NInVT, InOp0, in PromoteIntRes_EXTRACT_SUBVECTOR()
5993 ISD::EXTRACT_SUBVECTOR, dl, OutVT, Step1, in PromoteIntRes_EXTRACT_SUBVECTOR()
6001 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), OutVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
6016 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
6383 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()
H A DSelectionDAGDumper.cpp345 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
H A DSelectionDAG.cpp3105 case ISD::EXTRACT_SUBVECTOR: { in isSplatValue()
3572 case ISD::EXTRACT_SUBVECTOR: { in computeKnownBits()
5199 case ISD::EXTRACT_SUBVECTOR: { in ComputeNumSignBits()
5540 case ISD::EXTRACT_SUBVECTOR: in canCreateUndefOrPoison()
5836 case ISD::EXTRACT_SUBVECTOR: { in isKnownNeverNaN()
6220 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR || in foldCONCAT_VECTORS()
7775 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
7803 case ISD::EXTRACT_SUBVECTOR: { in getNode()
8085 if (N1.isUndef() && N2.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
12543 while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) in peekThroughExtractSubvectors()
[all …]
H A DSelectionDAGBuilder.cpp431 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, PartEVT, Val, in getCopyFromPartsVector()
818 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, in getCopyToPartsVector()
4174 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result, in visitShuffleVector()
4220 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src, in visitShuffleVector()
8183 DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index)); in visitIntrinsicCall()
12591 SubVecs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec, in visitVectorDeinterleave()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp203 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
466 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addMVEVectorTypes()
6306 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
8351 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8357 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8362 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8365 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
9838 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9840 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9842 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp340 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
651 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
2042 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
2127 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val, in convertArgType()
6614 Src0SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src0, in lowerLaneOp()
6619 Src1SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src1, in lowerLaneOp()
6623 Src2SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, SubVecVT, Src2, in lowerLaneOp()
7982 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, PackVT, in lowerVECTOR_SHUFFLE()
8007 SDValue SubVec0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, PackVT, SrcOp0, in lowerVECTOR_SHUFFLE()
8009 SDValue SubVec1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, PackVT, SrcOp1, in lowerVECTOR_SHUFFLE()
[all …]
H A DAMDGPUISelLowering.cpp460 ISD::EXTRACT_SUBVECTOR, in AMDGPUTargetLowering()
1435 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
1816 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in splitVector()
1819 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL, in splitVector()
1912 {DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, VT, WideLoad, in WidenOrSplitVectorLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp206 ISD::EXTRACT_SUBVECTOR}); in WebAssemblyTargetLowering()
2946 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performVectorExtendCombine()
3128 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, VecIdx); in extractSubVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp800 ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR, in RISCVTargetLowering()
929 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1110 ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, in RISCVTargetLowering()
1160 ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR, in RISCVTargetLowering()
1262 setOperationAction({ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR}, VT, in RISCVTargetLowering()
1426 ISD::EXTRACT_SUBVECTOR, ISD::VECTOR_REVERSE, in RISCVTargetLowering()
2342 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4691 if (V1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in foldConcatVector()
4692 V2.getOpcode() != ISD::EXTRACT_SUBVECTOR) in foldConcatVector()
4925 while (Parent.getOpcode() == ISD::EXTRACT_SUBVECTOR && in lowerVECTOR_SHUFFLEAsVSlidedown()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td850 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
858 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;

12