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Searched refs:EVEX (Results 1 – 25 of 30) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrRAOINT.td43 defm AADD : RaoInt<"add", "_EVEX">, EVEX, T_MAP4;
44 defm AAND : RaoInt<"and", "_EVEX">, EVEX, T_MAP4, PD;
45 defm AOR : RaoInt<"or", "_EVEX">, EVEX, T_MAP4, XD;
46 defm AXOR : RaoInt<"xor", "_EVEX">, EVEX, T_MAP4, XS;
H A DX86InstrAVX10.td66 EVEX, VVVV, Sched<[WriteFMAX]>;
72 EVEX, VVVV,
80 EVEX, VVVV, EVEX_B,
93 EVEX, VVVV, EVEX_B, EVEX_V512, Sched<[WriteFMAX]>;
169 AVX512AIi8Base, VEX_LIG, EVEX, VVVV, EVEX_CD8<64, CD8VT1>, REX_W;
171 AVX512PSIi8Base, VEX_LIG, EVEX, VVVV, EVEX_CD8<16, CD8VT1>, TA;
173 AVX512AIi8Base, VEX_LIG, EVEX, VVVV, EVEX_CD8<32, CD8VT1>;
212 Sched<[sched.ZMM]>, EVEX, EVEX_RC, EVEX_B;
226 Sched<[sched.ZMM]>, EVEX, EVEX_B;
236 EVEX, EVEX_V512;
[all …]
H A DX86InstrAVX512.td389 AVX512AIi8Base, EVEX, VVVV, Sched<[sched]>;
400 (iPTR imm))>, AVX512AIi8Base, EVEX, VVVV,
664 EVEX, VVVV, Sched<[SchedWriteFShuffle.XMM]>;
671 EVEX, VVVV, EVEX_CD8<32, CD8VT1>,
694 AVX512AIi8Base, EVEX, Sched<[SchedRR]>;
702 addr:$dst)]>, EVEX,
712 EVEX_K, EVEX, Sched<[SchedMR]>;
836 // smaller extract to enable EVEX->VEX.
869 // smaller extract to enable EVEX->VEX.
1013 EVEX, WIG, Sched<[WriteVecExtract]>;
[all …]
H A DX86InstrMisc.td168 []>, EVEX, VVVV, EVEX_B, T_MAP4;
171 []>, EVEX, VVVV, EVEX_B, T_MAP4, REX_W;
189 []>, EVEX, VVVV, EVEX_B, T_MAP4;
192 []>, EVEX, VVVV, EVEX_B, T_MAP4, REX_W;
1112 defm MOVBE16 : Movbe<0x60, Xi16, "_EVEX">, EVEX, T_MAP4, PD;
1113 defm MOVBE32 : Movbe<0x60, Xi32, "_EVEX">, EVEX, T_MAP4;
1114 defm MOVBE64 : Movbe<0x60, Xi64, "_EVEX">, EVEX, T_MAP4;
1121 EVEX, T_MAP4;
1124 EVEX, T_MAP4, DisassembleOnly;
1227 defm BLSR32 : Bls<"blsr", MRM1r, MRM1m, Xi32, "_EVEX">, EVEX;
[all …]
H A DX86InstrPredicates.td12 // EVEX. Not all X86 instructions are extended for EGPR. The following is an
19 // * EVEX space
20 // All instructions in the EVEX space can access the EGPR in their
24 // the REX2/EVEX prefix when EGPR is used, i.e. the opcode and opcode name are
29 // promoted into EVEX space. Encoding space changes after the promotion, opcode
H A DX86CompressEVEX.cpp181 if ((TSFlags & X86II::EncodingMask) != X86II::EVEX) in CompressEVEXImpl()
287 case X86II::EVEX: in CompressEVEXImpl()
H A DX86InstrAMX.td50 defm "" : AMX_TILE_COMMON<"_EVEX", HasEGPR>, EVEX, NoCD8;
363 defm T2RPNTLVW : T2RPNTLVW_Base<0x6e, 0x6f, "", "_EVEX">, T8, EVEX, NoCD8;
369 defm T2RPNTLVW : T2RPNTLVW_Base<0xf8, 0xf9, "RS", "_EVEX">, T_MAP5, EVEX, NoCD8;
534 defm TILELOADDRS : TILELOADDRS_Base<"_EVEX">, EVEX, NoCD8;
558 []>, TA,XS, EVEX, EVEX_V512;
562 []>, T8,XS, EVEX, VVVV, EVEX_V512;
638 []>, EVEX, VVVV, EVEX_V512, T8;
643 []>, EVEX, EVEX_V512, TA;
666 []>, TA,PD, EVEX, EVEX_V512;
670 []>, T8,PD, EVEX, VVVV, EVEX_V512;
H A DX86InstrVMX.td27 EVEX, NoCD8, T_MAP4, XS, WIG, Requires<[In64BitMode]>;
38 EVEX, NoCD8, T_MAP4, XS, WIG, Requires<[In64BitMode]>;
H A DX86InstrCMovSetCC.td42 []>, UseEFLAGS, EVEX, T_MAP4;
53 "cfcmov${cond}", unaryop_ndd_args, []>, UseEFLAGS, EVEX, T_MAP4;
H A DX86EvexToVex.cpp
H A DX86InstrArithmetic.td1387 defm ANDN32 : AndN<Xi32, X86and_flag, "_EVEX">, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>, Def…
1388 defm ANDN64 : AndN<Xi64, X86and_flag, "_EVEX">, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>, Def…
1389 defm ANDN32 : AndN<Xi32, null_frag, "_NF">, EVEX, EVEX_NF, Requires<[In64BitMode]>;
1390 defm ANDN64 : AndN<Xi64, null_frag, "_NF">, EVEX, EVEX_NF, Requires<[In64BitMode]>;
1434 EVEX, VVVV, Sched<[WriteIMulH, sched]>;
1439 EVEX, VVVV, Sched<mulx_rm_sched>;
1467 def ADCX32rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi32>, EVEX, T_MAP4, PD;
1468 def ADCX64rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi64>, EVEX, T_MAP4, PD;
1469 def ADOX32rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi32>, EVEX, T_MAP4, XS;
1470 def ADOX64rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi64>, EVEX, T_MAP4, XS;
[all …]
H A DX86InstrFMA3Info.cpp164 ((TSFlags & X86II::EncodingMask) == X86II::EVEX && in getFMA3Group()
H A DX86InstrSystem.td492 defm "" : Urdwrmsr<T_MAP4, "_EVEX">, EVEX;
580 [(int_x86_wrssd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4;
583 [(int_x86_wrssq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4;
586 [(int_x86_wrussd GR32:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD;
589 [(int_x86_wrussq GR64:$src, addr:$dst)]>, EVEX, NoCD8, T_MAP4, PD;
741 EVEX, NoCD8, T_MAP4, XS, WIG, Requires<[In64BitMode]>;
H A DX86ReplaceableInstrs.def405 // Special table for changing EVEX logic instructions to VEX.
406 // TODO: Should we run EVEX->VEX earlier?
H A DX86RegisterInfo.td97 // APX only, requires REX2 or EVEX.
213 // APX only, requires REX2 or EVEX.
260 // APX only, requires REX2 or EVEX.
302 // APX only, requires REX2 or EVEX.
H A DX86InstrConditionalCompare.td15 … m#"${cond}", "$dcf\t{$src2, $src1|$src1, $src2}" , []>, T_MAP4, EVEX, Requires<[In64BitMode]> {
H A DX86InstrUtils.td44 class EVEX { Encoding OpEnc = EncEVEX; }
119 class NF: T_MAP4, EVEX, EVEX_NF;
121 class PL: T_MAP4, EVEX, ExplicitEVEXPrefix;
123 class ZU: T_MAP4, EVEX, EVEX_B;
835 EVEX, VVVV, Requires<[HasAVX512]>;
H A DX86InstrFormats.td197 // Force the instruction to use REX2/VEX/EVEX encoding.
H A DX86FixupVectorConstants.cpp714 if ((MI.getDesc().TSFlags & X86II::EncodingMask) == X86II::EVEX) in processInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp41 enum PrefixKind { None, REX, REX2, XOP, VEX2, VEX3, EVEX }; enumerator
174 assert((!R2 || (Kind <= REX2 || Kind == EVEX)) && "invalid setting"); in setR2()
178 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting"); in setX2()
183 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting"); in setB2()
289 case EVEX: in determineOptimalKind()
324 case EVEX: in emit()
419 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; in isDispOrCDisp8()
1000 case X86II::EVEX: in emitVEXOpcodePrefix()
1001 Prefix.setLowerBound(EVEX); in emitVEXOpcodePrefix()
H A DX86BaseInfo.h825 EVEX = 3 << EncodingShift, enumerator
1264 if (Encoding == X86II::EVEX) in canUseApxExtendedReg()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DX86EVEX2VEXTablesEmitter.cpp
H A DX86RecognizableInstr.h174 enum { VEX = 1, XOP = 2, EVEX = 3 }; enumerator
H A DX86InstrMappingEmitter.cpp206 else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 && in emitCompressEVEXTable()
H A DX86ManualInstrMapping.def9 // This file defines all the entries in X86 EVEX compression tables that need

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