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Searched refs:ENIC_BUS_WRITE_4 (Results 1 – 8 of 8) sorted by relevance

/freebsd/sys/dev/enic/
H A Dvnic_cq.c20 ENIC_BUS_WRITE_4(cq->ctrl, CQ_RING_SIZE, cq->ring.desc_count); in vnic_cq_init()
21 ENIC_BUS_WRITE_4(cq->ctrl, CQ_FLOW_CONTROL_ENABLE, flow_control_enable); in vnic_cq_init()
22 ENIC_BUS_WRITE_4(cq->ctrl, CQ_COLOR_ENABLE, color_enable); in vnic_cq_init()
23 ENIC_BUS_WRITE_4(cq->ctrl, CQ_HEAD, cq_head); in vnic_cq_init()
24 ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL, cq_tail); in vnic_cq_init()
25 ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL_COLOR, cq_tail_color); in vnic_cq_init()
26 ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_ENABLE, interrupt_enable); in vnic_cq_init()
27 ENIC_BUS_WRITE_4(cq->ctrl, CQ_ENTRY_ENABLE, cq_entry_enable); in vnic_cq_init()
28 ENIC_BUS_WRITE_4(cq->ctrl, CQ_MESSAGE_ENABLE, cq_message_enable); in vnic_cq_init()
29 ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_OFFSET, interrupt_offset); in vnic_cq_init()
[all …]
H A Dvnic_wq.c20 ENIC_BUS_WRITE_4(wq->ctrl, TX_RING_SIZE, count); in vnic_wq_init_start()
21 ENIC_BUS_WRITE_4(wq->ctrl, TX_FETCH_INDEX, fetch_index); in vnic_wq_init_start()
22 ENIC_BUS_WRITE_4(wq->ctrl, TX_POSTED_INDEX, posted_index); in vnic_wq_init_start()
23 ENIC_BUS_WRITE_4(wq->ctrl, TX_CQ_INDEX, cq_index); in vnic_wq_init_start()
24 ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_INTR_ENABLE, error_interrupt_enable); in vnic_wq_init_start()
25 ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_INTR_OFFSET, error_interrupt_offset); in vnic_wq_init_start()
26 ENIC_BUS_WRITE_4(wq->ctrl, TX_ERROR_STATUS, 0); in vnic_wq_init_start()
50 ENIC_BUS_WRITE_4(wq->ctrl, TX_ENABLE, 1); in vnic_wq_enable()
57 ENIC_BUS_WRITE_4(wq->ctrl, TX_ENABLE, 0); in vnic_wq_disable()
84 ENIC_BUS_WRITE_4(wq->ctrl, TX_FETCH_INDEX, 0); in vnic_wq_clean()
[all …]
H A Dvnic_rq.c20 ENIC_BUS_WRITE_4(rq->ctrl, RX_RING_SIZE, count); in vnic_rq_init_start()
21 ENIC_BUS_WRITE_4(rq->ctrl, RX_CQ_INDEX, cq_index); in vnic_rq_init_start()
22 ENIC_BUS_WRITE_4(rq->ctrl, RX_ERROR_INTR_ENABLE, error_interrupt_enable); in vnic_rq_init_start()
23 ENIC_BUS_WRITE_4(rq->ctrl, RX_ERROR_INTR_OFFSET, error_interrupt_offset); in vnic_rq_init_start()
24 ENIC_BUS_WRITE_4(rq->ctrl, RX_ERROR_STATUS, 0); in vnic_rq_init_start()
25 ENIC_BUS_WRITE_4(rq->ctrl, RX_FETCH_INDEX, fetch_index); in vnic_rq_init_start()
26 ENIC_BUS_WRITE_4(rq->ctrl, RX_POSTED_INDEX, posted_index); in vnic_rq_init_start()
58 ENIC_BUS_WRITE_4(rq->ctrl, RX_ENABLE, 1); in vnic_rq_enable()
65 ENIC_BUS_WRITE_4(rq->ctrl, RX_ENABLE, 0); in vnic_rq_disable()
94 ENIC_BUS_WRITE_4(rq->ctrl, RX_POSTED_INDEX, fetch_index); in vnic_rq_clean()
H A Dvnic_intr.c34 ENIC_BUS_WRITE_4(intr->ctrl, INTR_COALESCING_TYPE, coalescing_type); in vnic_intr_init()
35 ENIC_BUS_WRITE_4(intr->ctrl, INTR_MASK_ON_ASSERTION, mask_on_assertion); in vnic_intr_init()
36 ENIC_BUS_WRITE_4(intr->ctrl, INTR_CREDITS, 0); in vnic_intr_init()
42 ENIC_BUS_WRITE_4(intr->ctrl, INTR_COALESCING_TIMER, in vnic_intr_coalescing_timer_set()
48 ENIC_BUS_WRITE_4(intr->ctrl, INTR_CREDITS, 0); in vnic_intr_clean()
H A Dvnic_intr.h48 ENIC_BUS_WRITE_4(intr->ctrl, INTR_MASK, 1); in vnic_intr_mask()
61 ENIC_BUS_WRITE_4(intr->ctrl, INTR_MASK, 0); in vnic_intr_unmask()
74 ENIC_BUS_WRITE_4(intr->ctrl, INTR_CREDIT_RETURN, int_credit_return); in vnic_intr_return_credits()
H A Denic_txrx.c160 ENIC_BUS_WRITE_4(wq->ctrl, TX_POSTED_INDEX, head_idx); in enic_isc_txd_flush()
293 ENIC_BUS_WRITE_4(rq->ctrl, RX_FETCH_INDEX, 0); in enic_isc_rxd_refill()
316 ENIC_BUS_WRITE_4(rq->ctrl, RX_POSTED_INDEX, pidx); in enic_isc_rxd_flush()
364 ENIC_BUS_WRITE_4(rq->ctrl, RX_POSTED_INDEX, rq->posted_index); in enic_initial_post_rx()
H A Denic.h38 #define ENIC_BUS_WRITE_4(res, index, value) \ macro
H A Dvnic_dev.c204 ENIC_BUS_WRITE_4(devcmd, DEVCMD_CMD, cmd); in _vnic_dev_cmd()