1*9c067b84SDoug Ambrisko /* SPDX-License-Identifier: BSD-3-Clause
2*9c067b84SDoug Ambrisko * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
3*9c067b84SDoug Ambrisko * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4*9c067b84SDoug Ambrisko */
5*9c067b84SDoug Ambrisko
6*9c067b84SDoug Ambrisko #include "enic.h"
7*9c067b84SDoug Ambrisko #include "vnic_dev.h"
8*9c067b84SDoug Ambrisko #include "vnic_cq.h"
9*9c067b84SDoug Ambrisko
vnic_cq_init(struct vnic_cq * cq,unsigned int flow_control_enable,unsigned int color_enable,unsigned int cq_head,unsigned int cq_tail,unsigned int cq_tail_color,unsigned int interrupt_enable,unsigned int cq_entry_enable,unsigned int cq_message_enable,unsigned int interrupt_offset,u64 cq_message_addr)10*9c067b84SDoug Ambrisko void vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,
11*9c067b84SDoug Ambrisko unsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,
12*9c067b84SDoug Ambrisko unsigned int cq_tail_color, unsigned int interrupt_enable,
13*9c067b84SDoug Ambrisko unsigned int cq_entry_enable, unsigned int cq_message_enable,
14*9c067b84SDoug Ambrisko unsigned int interrupt_offset, u64 cq_message_addr)
15*9c067b84SDoug Ambrisko {
16*9c067b84SDoug Ambrisko u64 paddr;
17*9c067b84SDoug Ambrisko
18*9c067b84SDoug Ambrisko paddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET;
19*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_8(cq->ctrl, CQ_RING_BASE, paddr);
20*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_RING_SIZE, cq->ring.desc_count);
21*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_FLOW_CONTROL_ENABLE, flow_control_enable);
22*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_COLOR_ENABLE, color_enable);
23*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_HEAD, cq_head);
24*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL, cq_tail);
25*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL_COLOR, cq_tail_color);
26*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_ENABLE, interrupt_enable);
27*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_ENTRY_ENABLE, cq_entry_enable);
28*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_MESSAGE_ENABLE, cq_message_enable);
29*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_INTR_OFFSET, interrupt_offset);
30*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_8(cq->ctrl, CQ_MESSAGE_ADDR, cq_message_addr);
31*9c067b84SDoug Ambrisko
32*9c067b84SDoug Ambrisko cq->interrupt_offset = interrupt_offset;
33*9c067b84SDoug Ambrisko }
34*9c067b84SDoug Ambrisko
vnic_cq_clean(struct vnic_cq * cq)35*9c067b84SDoug Ambrisko void vnic_cq_clean(struct vnic_cq *cq)
36*9c067b84SDoug Ambrisko {
37*9c067b84SDoug Ambrisko cq->to_clean = 0;
38*9c067b84SDoug Ambrisko cq->last_color = 0;
39*9c067b84SDoug Ambrisko
40*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_HEAD, 0);
41*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL, 0);
42*9c067b84SDoug Ambrisko ENIC_BUS_WRITE_4(cq->ctrl, CQ_TAIL_COLOR, 1);
43*9c067b84SDoug Ambrisko }
44