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Searched refs:EEW (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp170 uint8_t EEW; in getEEWAndEMUL() local
178 EEW = 8; in getEEWAndEMUL()
184 EEW = 16; in getEEWAndEMUL()
190 EEW = 32; in getEEWAndEMUL()
196 EEW = 64; in getEEWAndEMUL()
202 auto EMUL = RISCVVType::getSameRatioLMUL(SEW, LMUL, EEW); in getEEWAndEMUL()
203 if (!EEW) in getEEWAndEMUL()
205 return std::make_pair(EEW, *EMUL); in getEEWAndEMUL()
253 auto [EEW, EMUL] = getEEWAndEMUL(Opcode, VLMUL, SEW); in getSchedClassID()
254 RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, EMUL, EEW); in getSchedClassID()
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVTargetParser.cpp227 getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) { in getSameRatioLMUL() argument
229 unsigned EMULFixedPoint = (EEW * 8) / Ratio; in getSameRatioLMUL()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td241 // List of EEW.
762 int EEW> :
767 RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
778 int EEW> :
784 RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
796 int EEW> :
801 RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
812 int EEW> :
818 RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
830 int EEW>
[all...]
H A DRISCVInstrFormats.td72 // * Widening: The destination EEW is greater than the source EEW, the source
77 // * Narrowing: The destination EEW is smaller than the source EEW. The
H A DRISCVFeatures.td663 "with maximal 32 EEW)",
670 "with maximal 32 EEW and F extension)",
676 "with maximal 64 EEW)",
682 "with maximal 64 EEW and F extension)",
688 "with maximal 64 EEW, F and D extension)",
H A DRISCVInsertVSETVLI.cpp1064 if (std::optional<unsigned> EEW = getEEWForLoadStore(MI)) { in computeInfoForInstr() local
1065 assert(SEW == EEW && "Initial SEW doesn't match expected EEW"); in computeInfoForInstr()
H A DRISCVSchedSiFive7.td503 // TODO: The MxLists need to be filtered by EEW. We only need to support
504 // LMUL >= SEW_min/ELEN. Here, the smallest EEW prevents us from having MF8
H A DRISCVInstrInfoVVLPatterns.td2362 // vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*.
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVTargetParser.h122 getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);