| /freebsd/crypto/openssl/test/recipes/30-test_evp_data/ |
| H A D | evppkey_kas.txt | 25 PrivateKey=KAS-ECC-CDH_P-192_C0
32 PublicKey=KAS-ECC-CDH_P-192_C0-PUBLIC
38 PrivPubKeyPair = KAS-ECC-CDH_P-192_C0:KAS-ECC-CDH_P-192_C0-PUBLIC
41 PublicKey=KAS-ECC-CDH_P-192_C0-Peer-PUBLIC
48 Derive=KAS-ECC-CDH_P-192_C0
49 PeerKey=KAS-ECC-CDH_P-192_C0-Peer-PUBLIC
54 Derive=KAS-ECC-CDH_P-192_C0
56 PeerKey=KAS-ECC-CDH_P-192_C0-Peer-PUBLIC
59 PrivateKey=KAS-ECC-CDH_P-192_C1
66 PublicKey=KAS-ECC-CDH_P-192_C1-PUBLIC
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| H A D | evppkey_ecc.txt | 56 # ECC CDH Alice with Bob peer
63 # ECC CDH Bob with Alice peer
76 # ECC CDH Bob with Malice peer
84 # ECC CDH Alice with Malice peer
134 # ECC CDH Alice with Bob peer
141 # ECC CDH Bob with Alice peer
154 # ECC CDH Bob with Malice peer
162 # ECC CDH Alice with Malice peer
212 # ECC CDH Alice with Bob peer
219 # ECC CDH Bob with Alice peer
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| H A D | evppkey_mismatch.txt | 34 PublicKey=KAS-ECC-CDH_K-163_C0-PUBLIC
81 PrivPubKeyPair = RSA-2048:KAS-ECC-CDH_K-163_C0-PUBLIC
84 PrivPubKeyPair = Alice-25519:KAS-ECC-CDH_K-163_C0-PUBLIC
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| /freebsd/sys/contrib/device-tree/Bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
15 L2 Cache ECC
18 - reg : Address and size for ECC error interrupt clear registers.
22 On Chip RAM ECC
25 - reg : Address and size for ECC error interrupt clear registers.
52 Arria10 SoCFPGA ECC Manager
53 The Arria10 SoC ECC Manager handles the IRQs for each peripheral
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| H A D | aspeed-sdram-edac.txt | 3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
10 Note, the bootloader must configure ECC mode in the memory controller.
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | synopsys.txt | 3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
9 These both ECC controllers correct single bit ECC errors and detect double bit
10 ECC errors.
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | gpmc-nand.txt | 10 For NAND specific properties such as ECC modes or bus width, please refer to
27 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
34 "bch16" 16-bit BCH ECC code
35 Refer below "How to select correct ECC scheme for your device ?"
47 locating ECC errors for BCHx algorithms. SoC devices which have
49 Using ELM for ECC error correction frees some CPU cycles.
105 How to select correct ECC scheme for your device ?
107 Higher ECC scheme usually means better protection against bit-flips and
108 increased system lifetime. However, selection of ECC scheme is dependent
121 Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
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| H A D | mtk-nand.txt | 5 the nand controller interface driver and the ECC engine driver.
23 - ecc-engine: Required ECC Engine node.
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
155 2) ECC Engine:
163 - reg: Base physical address and size of ECC.
164 - interrupts: Interrupts of ECC.
165 - clocks: ECC required clocks.
166 - clock-names: ECC clocks internal name.
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| H A D | nvidia-tegra20-nand.txt | 27 - nand-ecc-algo: string, algorithm of NAND ECC.
28 Supported values with "hw" ECC mode are: "rs", "bch".
32 per ECC step (always 512). Supported strength using HW ECC
37 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
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| H A D | gpmi-nand.txt | 32 - fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC
33 strength required. The required ECC strength is
39 ECC scheme.
51 per ECC step. Needs to be a multiple of 2.
53 that are covered by a single ECC step. The driver
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| H A D | hisi504-nand.txt | 17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
20 The following ECC strength and step size are currently supported:
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| H A D | atmel-nand.txt | 6 The NAND controller might be connected to an ECC engine.
51 * ECC engine (PMECC) bindings:
120 and hardware ECC controller if available.
121 If the hardware ECC is PMECC, it should contain address and size for
138 - atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
140 - atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
143 - atmel,pmecc-sector-size : sector size for ECC computation. Supported values
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| H A D | marvell-nand.txt | 47 - nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
49 not using hardware ECC. Howerver, it may be added when using hardware
50 ECC for clarification but will be ignored by the driver because ECC
59 patterns described in AN-379, "Marvell SoC NFC ECC".
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| /freebsd/sys/contrib/device-tree/Bindings/reserved-memory/ |
| H A D | ramoops.txt | 10 as kernel log messages, or for optional ECC error-correction data. The total
30 - ecc-size: enables ECC support and specifies ECC buffer size in bytes
31 (defaults to 0: no ECC)
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| /freebsd/secure/caroot/trusted/ |
| H A D | GlobalSign_ECC_Root_CA_-_R4.pem | 2 ## GlobalSign ECC Root CA - R4
20 Issuer: OU = GlobalSign ECC Root CA - R4, O = GlobalSign, CN = GlobalSign
24 Subject: OU = GlobalSign ECC Root CA - R4, O = GlobalSign, CN = GlobalSign
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| H A D | AffirmTrust_Premium_ECC.pem | 2 ## AffirmTrust Premium ECC
19 Issuer: C = US, O = AffirmTrust, CN = AffirmTrust Premium ECC
23 Subject: C = US, O = AffirmTrust, CN = AffirmTrust Premium ECC
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| H A D | DigiCert_TLS_ECC_P384_Root_G5.pem | 2 ## DigiCert TLS ECC P384 Root G5
20 Issuer: C = US, O = "DigiCert, Inc.", CN = DigiCert TLS ECC P384 Root G5
24 Subject: C = US, O = "DigiCert, Inc.", CN = DigiCert TLS ECC P384 Root G5
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| H A D | Hellenic_Academic_and_Research_Institutions_ECC_RootCA_2015.pem | 2 ## Hellenic Academic and Research Institutions ECC RootCA 2015
19 …arch Institutions Cert. Authority, CN = Hellenic Academic and Research Institutions ECC RootCA 2015
23 …arch Institutions Cert. Authority, CN = Hellenic Academic and Research Institutions ECC RootCA 2015
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| H A D | Trustwave_Global_ECC_P256_Certification_Authority.pem | 2 ## Trustwave Global ECC P256 Certification Authority
20 …linois, L = Chicago, O = "Trustwave Holdings, Inc.", CN = Trustwave Global ECC P256 Certification …
24 …linois, L = Chicago, O = "Trustwave Holdings, Inc.", CN = Trustwave Global ECC P256 Certification …
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| H A D | CommScope_Public_Trust_ECC_Root-01.pem | 2 ## CommScope Public Trust ECC Root-01
20 Issuer: C = US, O = CommScope, CN = CommScope Public Trust ECC Root-01
24 Subject: C = US, O = CommScope, CN = CommScope Public Trust ECC Root-01
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| H A D | GlobalSign_ECC_Root_CA_-_R5.pem | 2 ## GlobalSign ECC Root CA - R5
20 Issuer: OU = GlobalSign ECC Root CA - R5, O = GlobalSign, CN = GlobalSign
24 Subject: OU = GlobalSign ECC Root CA - R5, O = GlobalSign, CN = GlobalSign
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| H A D | Microsoft_ECC_Root_Certificate_Authority_2017.pem | 2 ## Microsoft ECC Root Certificate Authority 2017
20 … Issuer: C = US, O = Microsoft Corporation, CN = Microsoft ECC Root Certificate Authority 2017
24 … Subject: C = US, O = Microsoft Corporation, CN = Microsoft ECC Root Certificate Authority 2017
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| H A D | Atos_TrustedRoot_Root_CA_ECC_TLS_2021.pem | 2 ## Atos TrustedRoot Root CA ECC TLS 2021
20 Issuer: CN = Atos TrustedRoot Root CA ECC TLS 2021, O = Atos, C = DE
24 Subject: CN = Atos TrustedRoot Root CA ECC TLS 2021, O = Atos, C = DE
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| H A D | COMODO_ECC_Certification_Authority.pem | 2 ## COMODO ECC Certification Authority
20 …, ST = Greater Manchester, L = Salford, O = COMODO CA Limited, CN = COMODO ECC Certification Autho…
24 …, ST = Greater Manchester, L = Salford, O = COMODO CA Limited, CN = COMODO ECC Certification Autho…
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| /freebsd/crypto/openssl/doc/man3/ |
| H A D | SSL_CTX_set_security_level.pod | 77 DSA and DH keys shorter than 1024 bits and ECC keys shorter than 160 bits
87 shorter than 2048 bits and ECC keys shorter than 224 bits are prohibited.
94 shorter than 3072 bits and ECC keys shorter than 256 bits are prohibited.
102 DH keys shorter than 7680 bits and ECC keys shorter than 384 bits are
109 shorter than 15360 bits and ECC keys shorter than 512 bits are prohibited.
132 cipher suite encryption algorithms, supported ECC curves, supported
141 Some security levels require large key sizes for non-ECC public key
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