Lines Matching refs:ECC

1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
15 L2 Cache ECC
18 - reg : Address and size for ECC error interrupt clear registers.
22 On Chip RAM ECC
25 - reg : Address and size for ECC error interrupt clear registers.
52 Arria10 SoCFPGA ECC Manager
53 The Arria10 SoC ECC Manager handles the IRQs for each peripheral
60 containing the ECC manager registers.
65 - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
71 L2 Cache ECC
74 - reg : Address and size for ECC error interrupt clear registers.
78 On-Chip RAM ECC
81 - reg : Address and size for ECC block registers.
85 Ethernet FIFO ECC
88 - reg : Address and size for ECC block registers.
93 NAND FIFO ECC
96 - reg : Address and size for ECC block registers.
101 DMA FIFO ECC
104 - reg : Address and size for ECC block registers.
109 USB FIFO ECC
112 - reg : Address and size for ECC block registers.
117 QSPI FIFO ECC
120 - reg : Address and size for ECC block registers.
125 SDMMC FIFO ECC
128 - reg : Address and size for ECC block registers.
235 Stratix10 SoCFPGA ECC Manager (ARM64)
236 The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
237 in a shared register similar to the Arria10. However, Stratix10 ECC
246 containing the ECC manager registers.
248 - interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
256 SDRAM ECC
261 On-Chip RAM ECC
264 - reg : Address and size for ECC block registers.
268 Ethernet FIFO ECC
271 - reg : Address and size for ECC block registers.
275 NAND FIFO ECC
278 - reg : Address and size for ECC block registers.
282 DMA FIFO ECC
285 - reg : Address and size for ECC block registers.
289 USB FIFO ECC
292 - reg : Address and size for ECC block registers.
296 SDMMC FIFO ECC
299 - reg : Address and size for ECC block registers.