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Searched refs:DstRC (Results 1 – 25 of 59) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp216 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses() local
220 return std::pair(SrcRC, DstRC); in getCopyRegClasses()
224 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy() argument
226 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
231 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy() argument
233 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
234 TRI.hasVectorRegisters(DstRC); in isSGPRToVGPRCopy()
299 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
300 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
302 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
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H A DAMDGPUInstructionSelector.cpp112 const TargetRegisterClass *DstRC in constrainCopyLikeIntrin() local
116 if (!DstRC || DstRC != SrcRC) in constrainCopyLikeIntrin()
119 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
610 const TargetRegisterClass *DstRC = in selectG_EXTRACT() local
612 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_EXTRACT()
649 const TargetRegisterClass *DstRC = in selectG_MERGE_VALUES() local
651 if (!DstRC) in selectG_MERGE_VALUES()
654 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES()
668 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_MERGE_VALUES()
710 const TargetRegisterClass *DstRC = in selectG_UNMERGE_VALUES() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
H A DX86InstrMMX.td123 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
126 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
127 [(set DstRC:$dst, (Int SrcRC:$src))], d>,
129 def rm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
130 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
135 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
137 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
138 (ins DstRC:$src1, SrcRC:$src2), asm,
139 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
141 def rm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp114 const TargetRegisterClass *DstRC,
299 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy() local
301 if (SrcRC != DstRC) { in selectCopy()
303 Register ExtSrc = MRI.createVirtualRegister(DstRC); in selectCopy()
327 const TargetRegisterClass *DstRC = in selectCopy() local
337 if (DstRC != SrcRC) { in selectCopy()
338 I.getOperand(1).setSubReg(getSubRegIndex(DstRC)); in selectCopy()
347 if (!OldRC || !DstRC->hasSubClassEq(OldRC)) { in selectCopy()
348 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
795 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, in canTurnIntoCOPY() argument
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp69 const TargetRegisterClass *DstRC, in isCrossCopy() argument
74 if (DstRC == SrcRC) in isCrossCopy()
99 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
102 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
104 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
105 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local
355 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
454 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
455 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO); in isUndefInput()
H A DMachineCombiner.cpp174 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
175 return TRI->getMatchingSuperRegClass(SrcRC, DstRC, SrcSub) != nullptr; in isTransientMI()
183 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
184 return SrcRC->hasSuperClassEq(DstRC) || SrcRC->hasSubClassEq(DstRC); in isTransientMI()
191 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
192 return DstRC->contains(Src); in isTransientMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp129 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in foldSimpleCrossClassCopies() local
131 if (SrcRC == DstRC) in foldSimpleCrossClassCopies()
135 if (SrcRC->hasSubClass(DstRC)) { in foldSimpleCrossClassCopies()
145 if (!MRI.constrainRegClass(Src, DstRC, /* MinNumRegs */ 25)) in foldSimpleCrossClassCopies()
147 } else if (DstRC->hasSubClass(SrcRC)) { in foldSimpleCrossClassCopies()
H A DAArch64InstructionSelector.cpp149 const TargetRegisterClass *DstRC,
1024 const TargetRegisterClass *DstRC; in selectCopy() local
1025 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI); in selectCopy()
1027 if (!DstRC) { in selectCopy()
1042 const TypeSize DstSize = TRI.getRegSizeInBits(*DstRC); in selectCopy()
1050 getSubRegForClass(DstRC, TRI, SubReg); in selectCopy()
1054 copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg); in selectCopy()
1061 copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg); in selectCopy()
1087 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
3296 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select() local
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DFastISelEmitter.cpp211 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local
286 if (DstRC) { in initialize()
287 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize()
290 DstRC = RC; in initialize()
475 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
483 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns()
484 if (!DstRC) in collectPatterns()
526 DstRC)) in collectPatterns()
573 DstRC, std::move(SubRegNo), std::move(PhysRegInputs), in collectPatterns()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp251 auto DstRC = MRI.getRegClass(DstReg); in selectMachineFunction() local
252 if (SrcRC == DstRC) { in selectMachineFunction()
371 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in selectInstr() local
372 if (DstRC) in selectInstr()
373 MRI.setRegClass(SrcReg, DstRC); in selectInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp110 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local
117 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
H A DPPCVSXSwapRemoval.cpp922 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local
923 Register NewVReg = MRI->createVirtualRegister(DstRC); in handleSpecialSwappables()
936 if (DstRC == &PPC::VRRCRegClass) { in handleSpecialSwappables()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMips32r6InstrInfo.td659 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
662 dag OutOperandList = (outs DstRC:$rs);
670 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
674 dag OutOperandList = (outs DstRC:$fs);
676 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
682 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
684 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
685 dag OutOperandList = (outs DstRC:$fs);
695 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
698 dag OutOperandList = (outs DstRC:$impl);
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H A DMipsInstrFPU.td128 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
135 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
162 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
165 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
169 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h55 unsigned SubReg, const TargetRegisterClass *DstRC,
H A DAVRRegisterInfo.cpp310 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument
316 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, in shouldCoalesce()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
H A DHexagonRegisterInfo.cpp350 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument
361 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp153 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
158 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
162 DstRC = UseRC; in EmitCopyFromReg()
164 DstRC = SrcRC; in EmitCopyFromReg()
172 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg()
636 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
638 Register NewVReg = MRI->createVirtualRegister(DstRC); in EmitCopyToRegClassNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.h174 const TargetRegisterClass *DstRC,
H A DSystemZRegisterInfo.cpp386 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
394 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64) && in shouldCoalesce()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp1013 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectCopy() local
1015 assert(DstRC && in selectCopy()
1021 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) { in selectCopy()
1036 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectImplicitDef() local
1039 assert(DstRC && in selectImplicitDef()
1042 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) { in selectImplicitDef()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h157 const TargetRegisterClass *DstRC,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h149 unsigned SubReg, const TargetRegisterClass *DstRC,

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