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Searched refs:DstRC (Results 1 – 25 of 55) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp202 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses() local
206 return std::pair(SrcRC, DstRC); in getCopyRegClasses()
210 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy() argument
212 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
217 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy() argument
219 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
220 TRI.hasVectorRegisters(DstRC); in isSGPRToVGPRCopy()
285 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
286 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
288 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
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H A DAMDGPUInstructionSelector.cpp112 const TargetRegisterClass *DstRC in constrainCopyLikeIntrin() local
116 if (!DstRC || DstRC != SrcRC) in constrainCopyLikeIntrin()
119 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
512 const TargetRegisterClass *DstRC = in selectG_EXTRACT() local
514 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_EXTRACT()
551 const TargetRegisterClass *DstRC = in selectG_MERGE_VALUES() local
553 if (!DstRC) in selectG_MERGE_VALUES()
556 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES()
570 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_MERGE_VALUES()
612 const TargetRegisterClass *DstRC = in selectG_UNMERGE_VALUES() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
H A DX86InstrMMX.td123 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
126 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
127 [(set DstRC:$dst, (Int SrcRC:$src))], d>,
129 def rm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
130 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
135 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
137 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
138 (ins DstRC:$src1, SrcRC:$src2), asm,
139 [(set DstRC:$dst, (Int DstRC
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp112 const TargetRegisterClass *DstRC,
295 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy() local
297 if (SrcRC != DstRC) { in selectCopy()
299 Register ExtSrc = MRI.createVirtualRegister(DstRC); in selectCopy()
323 const TargetRegisterClass *DstRC = in selectCopy() local
333 if (DstRC != SrcRC) { in selectCopy()
334 I.getOperand(1).setSubReg(getSubRegIndex(DstRC)); in selectCopy()
343 if (!OldRC || !DstRC->hasSubClassEq(OldRC)) { in selectCopy()
344 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
767 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, in canTurnIntoCOPY() argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp69 const TargetRegisterClass *DstRC, in isCrossCopy() argument
74 if (DstRC == SrcRC) in isCrossCopy()
99 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
102 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
104 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
105 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
354 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local
355 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
447 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
448 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO); in isUndefInput()
H A DMachineCombiner.cpp177 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
178 return TRI->getMatchingSuperRegClass(SrcRC, DstRC, SrcSub) != nullptr; in isTransientMI()
186 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
187 return SrcRC->hasSuperClassEq(DstRC) || SrcRC->hasSubClassEq(DstRC); in isTransientMI()
194 auto DstRC = MRI->getRegClass(Dst); in isTransientMI() local
195 return DstRC->contains(Src); in isTransientMI()
H A DPeepholeOptimizer.cpp520 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
521 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
522 if (!DstRC) in INITIALIZE_PASS_DEPENDENCY()
627 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp134 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in foldSimpleCrossClassCopies() local
136 if (SrcRC == DstRC) in foldSimpleCrossClassCopies()
140 if (SrcRC->hasSubClass(DstRC)) { in foldSimpleCrossClassCopies()
150 if (!MRI.constrainRegClass(Src, DstRC, /* MinNumRegs */ 25)) in foldSimpleCrossClassCopies()
152 } else if (DstRC->hasSubClass(SrcRC)) { in foldSimpleCrossClassCopies()
H A DAArch64InstructionSelector.cpp149 const TargetRegisterClass *DstRC,
1016 const TargetRegisterClass *DstRC; in selectCopy() local
1017 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI); in selectCopy()
1019 if (!DstRC) { in selectCopy()
1034 const TypeSize DstSize = TRI.getRegSizeInBits(*DstRC); in selectCopy()
1042 getSubRegForClass(DstRC, TRI, SubReg); in selectCopy()
1046 copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg); in selectCopy()
1053 copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg); in selectCopy()
1079 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
3161 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp178 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction() local
179 if (DstRC) in runOnMachineFunction()
180 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
241 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local
242 if (SrcRC == DstRC) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DFastISelEmitter.cpp219 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local
296 if (DstRC) { in initialize()
297 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize()
300 DstRC = RC; in initialize()
494 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
502 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns()
503 if (!DstRC) in collectPatterns()
545 DstRC)) in collectPatterns()
593 DstRC, SubRegNo, PhysRegInputs, PredicateCheck); in collectPatterns()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local
127 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
H A DPPCVSXSwapRemoval.cpp924 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local
925 Register NewVReg = MRI->createVirtualRegister(DstRC); in handleSpecialSwappables()
938 if (DstRC == &PPC::VRRCRegClass) { in handleSpecialSwappables()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMips32r6InstrInfo.td659 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
662 dag OutOperandList = (outs DstRC:$rs);
670 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
674 dag OutOperandList = (outs DstRC:$fs);
676 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
682 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
684 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
685 dag OutOperandList = (outs DstRC:$fs);
695 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
698 dag OutOperandList = (outs DstRC:$impl);
[all …]
H A DMipsInstrFPU.td128 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
135 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
162 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
165 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
169 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.h55 unsigned SubReg, const TargetRegisterClass *DstRC,
H A DAVRRegisterInfo.cpp315 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument
321 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, in shouldCoalesce()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
H A DHexagonRegisterInfo.cpp355 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument
366 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp154 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
159 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
163 DstRC = UseRC; in EmitCopyFromReg()
165 DstRC = SrcRC; in EmitCopyFromReg()
173 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg()
642 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
644 Register NewVReg = MRI->createVirtualRegister(DstRC); in EmitCopyToRegClassNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.h173 const TargetRegisterClass *DstRC,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h142 unsigned SubReg, const TargetRegisterClass *DstRC,
H A DAArch64RegisterInfo.cpp1068 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument
1073 ((DstRC->getID() == AArch64::GPR64RegClassID) || in shouldCoalesce()
1074 (DstRC->getID() == AArch64::GPR64commonRegClassID)) && in shouldCoalesce()
1103 (AArch64::ZPRRegClass.hasSubClassEq(DstRC) || in shouldCoalesce()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp896 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectCopy() local
898 assert(DstRC && in selectCopy()
904 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
919 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank( in selectImplicitDef() local
922 assert(DstRC && in selectImplicitDef()
925 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectImplicitDef()

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