| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 723 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping() local
725 if (!DstRB) in getInstrMapping()
726 DstRB = SrcRB; in getInstrMapping()
728 SrcRB = DstRB; in getInstrMapping()
731 assert(DstRB && SrcRB && "Both RegBank were nullptr"); in getInstrMapping()
734 DefaultMappingID, copyCost(*DstRB, *SrcRB, Size), in getInstrMapping()
735 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
748 const RegisterBank &DstRB = in getInstrMapping() local
753 DefaultMappingID, copyCost(DstRB, SrcRB, Size), in getInstrMapping()
754 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
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| H A D | AArch64InstructionSelector.cpp | 321 const RegisterBank &DstRB, LLT ScalarTy,
2865 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
2866 assert(SrcRB.getID() == DstRB.getID() && "Wrong extract regbank!"); in select()
2883 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB); in select()
3286 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
3289 if (DstRB.getID() != SrcRB.getID()) { in select()
3295 if (DstRB.getID() == AArch64::GPRRegBankID) { in select()
3296 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select()
3327 } else if (DstRB.getID() == AArch64::FPRRegBankID) { in select()
3337 DstReg, DstRB, LLT::scalar(DstTy.getSizeInBits()), SrcReg, 0, MIB); in select()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBankInfo.cpp | 210 const RegisterBank &DstRB = DstIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping() local
214 MappingID, Cost, getCopyMapping(DstRB.getID(), SrcRB.getID(), DstSize), in getInstrMapping()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 392 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR() local
393 if (DstRB->getID() != AMDGPU::SGPRRegBankID && in selectG_AND_OR_XOR()
394 DstRB->getID() != AMDGPU::VCCRegBankID) in selectG_AND_OR_XOR()
397 bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID && in selectG_AND_OR_XOR()
419 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB() local
420 const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID; in selectG_ADD_SUB()
1568 auto DstRB = MRI.getRegBankOrNull(MI->getOperand(0).getReg()); in isLaneMaskFromSameBlock() local
1570 if (DstRB && SrcRB && DstRB->getID() == AMDGPU::VCCRegBankID && in isLaneMaskFromSameBlock()
1684 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectGroupStaticSize() local
1685 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ? in selectGroupStaticSize()
[all …]
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| H A D | AMDGPURegBankLegalizeHelper.cpp | 65 const RegisterBank *DstRB = MRI.getRegBankOrNull(Dst); in splitLoad() local
82 auto LoadPart = B.buildLoad({DstRB, PartTy}, BasePlusOffset, *OffsetMMO); in splitLoad()
98 auto Unmerge = B.buildUnmerge({DstRB, MergeTy}, Reg); in splitLoad()
114 const RegisterBank *DstRB = MRI.getRegBankOrNull(Dst); in widenLoad() local
118 auto WideLoad = B.buildLoad({DstRB, WideTy}, Base, *WideMMO); in widenLoad()
124 auto Unmerge = B.buildUnmerge({DstRB, MergeTy}, WideLoad); in widenLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 830 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt() local
833 if (DstRB.getID() != SrcRB.getID()) { in selectTruncOrPtrToInt()
839 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
851 if (DstRB.getID() != X86::GPRRegBankID) in selectTruncOrPtrToInt()
959 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext() local
962 assert(DstRB.getID() == SrcRB.getID() && in selectAnyext()
968 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext()
977 if (DstRB.getID() != X86::GPRRegBankID) in selectAnyext()
1209 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectUAddSub() local
1210 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectUAddSub()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 1204 const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI); in verifyPreISelGenericInstruction() local
1207 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) { in verifyPreISelGenericInstruction()
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