| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 712 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping() local
714 if (!DstRB) in getInstrMapping()
715 DstRB = SrcRB; in getInstrMapping()
717 SrcRB = DstRB; in getInstrMapping()
720 assert(DstRB && SrcRB && "Both RegBank were nullptr"); in getInstrMapping()
723 DefaultMappingID, copyCost(*DstRB, *SrcRB, Size), in getInstrMapping()
724 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
737 const RegisterBank &DstRB = in getInstrMapping() local
742 DefaultMappingID, copyCost(DstRB, SrcRB, Size), in getInstrMapping()
743 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
|
| H A D | AArch64InstructionSelector.cpp | 321 const RegisterBank &DstRB, LLT ScalarTy,
2736 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
2737 assert(SrcRB.getID() == DstRB.getID() && "Wrong extract regbank!"); in select()
2754 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB); in select()
3151 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
3154 if (DstRB.getID() != SrcRB.getID()) { in select()
3160 if (DstRB.getID() == AArch64::GPRRegBankID) { in select()
3161 const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(DstTy, DstRB); in select()
3192 } else if (DstRB.getID() == AArch64::FPRRegBankID) { in select()
3202 DstReg, DstRB, LLT::scalar(DstTy.getSizeInBits()), SrcReg, 0, MIB); in select()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 294 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR() local
295 if (DstRB->getID() != AMDGPU::SGPRRegBankID && in selectG_AND_OR_XOR()
296 DstRB->getID() != AMDGPU::VCCRegBankID) in selectG_AND_OR_XOR()
299 bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID && in selectG_AND_OR_XOR()
321 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB() local
322 const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID; in selectG_ADD_SUB()
1478 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectGroupStaticSize() local
1479 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ? in selectGroupStaticSize()
2201 const RegisterBank *DstRB; in selectG_TRUNC() local
2205 DstRB = SrcRB; in selectG_TRUNC()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/ |
| H A D | PPCRegisterBankInfo.cpp | 229 const RegisterBank &DstRB = DstIsGPR ? PPC::GPRRegBank : PPC::VECRegBank; in getInstrMapping() local
233 MappingID, Cost, getCopyMapping(DstRB.getID(), SrcRB.getID(), DstSize), in getInstrMapping()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 802 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt() local
805 if (DstRB.getID() != SrcRB.getID()) { in selectTruncOrPtrToInt()
811 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
823 if (DstRB.getID() != X86::GPRRegBankID) in selectTruncOrPtrToInt()
931 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext() local
934 assert(DstRB.getID() == SrcRB.getID() && in selectAnyext()
940 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext()
949 if (DstRB.getID() != X86::GPRRegBankID) in selectAnyext()
1169 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectUAddSub() local
1170 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectUAddSub()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineVerifier.cpp | 1162 const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI); in verifyPreISelGenericInstruction() local
1165 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) { in verifyPreISelGenericInstruction()
|