294   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_AND_OR_XOR()  local
295   if (DstRB->getID() != AMDGPU::SGPRRegBankID &&  in selectG_AND_OR_XOR()
296       DstRB->getID() != AMDGPU::VCCRegBankID)  in selectG_AND_OR_XOR()
299   bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID &&  in selectG_AND_OR_XOR()
321   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_ADD_SUB()  local
322   const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID;  in selectG_ADD_SUB()
1478   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectGroupStaticSize()  local
1479   unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ?  in selectGroupStaticSize()
2201   const RegisterBank *DstRB;  in selectG_TRUNC()  local
2205     DstRB = SrcRB;  in selectG_TRUNC()
2207     DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_TRUNC()
2208     if (SrcRB != DstRB)  in selectG_TRUNC()
2212   const bool IsVALU = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_TRUNC()
2220       TRI.getRegClassForSizeOnBank(DstSize, *DstRB);  in selectG_TRUNC()
2506   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);  in selectG_FPEXT()  local
2507   if (DstRB->getID() != AMDGPU::SGPRRegBankID)  in selectG_FPEXT()
2544   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_CONSTANT()  local
2545   const bool IsSgpr = DstRB->getID() == AMDGPU::SGPRRegBankID;  in selectG_CONSTANT()
2548   if (DstRB->getID() == AMDGPU::VCCRegBankID) {  in selectG_CONSTANT()
2622   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);  in selectG_FNEG()  local
2623   if (DstRB->getID() != AMDGPU::SGPRRegBankID ||  in selectG_FNEG()
2668   const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI);  in selectG_FABS()  local
2669   if (DstRB->getID() != AMDGPU::SGPRRegBankID ||  in selectG_FABS()
2886   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_GLOBAL_VALUE()  local
2887   const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_GLOBAL_VALUE()
2905   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_PTRMASK()  local
2908   const bool IsVGPR = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectG_PTRMASK()
2909   if (DstRB != SrcRB) // Should only happen for hand written MIR.  in selectG_PTRMASK()
2935   const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB);  in selectG_PTRMASK()
3044   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectG_EXTRACT_VECTOR_ELT()  local
3056       TRI.getRegClassForTypeOnBank(DstTy, *DstRB);  in selectG_EXTRACT_VECTOR_ELT()
3449   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);  in selectWaveAddress()  local
3450   const bool IsVALU = DstRB->getID() == AMDGPU::VGPRRegBankID;  in selectWaveAddress()