| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | IntegerDivision.cpp | 407 bool llvm::expandDivision(BinaryOperator *Div) { in expandDivision() argument
408 assert((Div->getOpcode() == Instruction::SDiv || in expandDivision()
409 Div->getOpcode() == Instruction::UDiv) && in expandDivision()
412 IRBuilder<> Builder(Div); in expandDivision()
414 assert(!Div->getType()->isVectorTy() && "Div over vectors not supported"); in expandDivision()
417 if (Div->getOpcode() == Instruction::SDiv) { in expandDivision()
419 Value *Quotient = generateSignedDivisionCode(Div->getOperand(0), in expandDivision()
420 Div->getOperand(1), Builder); in expandDivision()
423 bool IsInsertPoint = Div->getIterator() == Builder.GetInsertPoint(); in expandDivision()
424 Div->replaceAllUsesWith(Quotient); in expandDivision()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/ |
| H A D | IntegerDivision.h | 41 bool expandDivision(BinaryOperator* Div);
62 bool expandDivisionUpTo32Bits(BinaryOperator *Div);
68 bool expandDivisionUpTo64Bits(BinaryOperator *Div);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.cpp | 359 int64_t Div = 0; in generateInstSeq() local
364 Div = 3; in generateInstSeq()
367 Div = 5; in generateInstSeq()
370 Div = 9; in generateInstSeq()
374 if (Div > 0) { in generateInstSeq()
375 generateInstSeqImpl(Val / Div, STI, TmpSeq); in generateInstSeq()
384 Div = 0; in generateInstSeq()
386 Div = 3; in generateInstSeq()
389 Div = 5; in generateInstSeq()
392 Div = 9; in generateInstSeq()
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
| H A D | NVPTX.cpp | 145 const unsigned Div = std::min<unsigned>(MaxSize, Alignment); in coerceToIntArrayWithLimit() local
146 llvm::Type *IntType = llvm::Type::getIntNTy(getVMContext(), Div); in coerceToIntArrayWithLimit()
147 const uint64_t NumElements = (Size + Div - 1) / Div; in coerceToIntArrayWithLimit()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | DivRemPairs.cpp | 56 Instruction *Div; in matchExpandedRem() local
61 m_Instruction(Div)), in matchExpandedRem()
66 M.Key.SignedOp = Div->getOpcode() == Instruction::SDiv; in matchExpandedRem()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineMulDivRem.cpp | 398 BinaryOperator *Div = dyn_cast<BinaryOperator>(Op0); in visitMul() local
399 if (!Div || (Div->getOpcode() != Instruction::UDiv && in visitMul()
400 Div->getOpcode() != Instruction::SDiv)) { in visitMul()
402 Div = dyn_cast<BinaryOperator>(Op1); in visitMul()
405 if (Div && Div->hasOneUse() && in visitMul()
406 (Div->getOperand(1) == Y || Div->getOperand(1) == Neg) && in visitMul()
407 (Div->getOpcode() == Instruction::UDiv || in visitMul()
408 Div->getOpcode() == Instruction::SDiv)) { in visitMul()
409 Value *X = Div->getOperand(0), *DivOp1 = Div->getOperand(1); in visitMul()
412 if (Div->isExact()) { in visitMul()
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| H A D | InstCombineAddSub.cpp | 1178 Value *Div, *Rem; in SimplifyAddWithRemainder() local
1180 if (!LHS->hasOneUse() || !MatchMul(LHS, Div, C1)) in SimplifyAddWithRemainder()
1181 Div = LHS, C1 = APInt(I.getType()->getScalarSizeInBits(), 1); in SimplifyAddWithRemainder()
1184 if (match(Div, m_IRem(m_Value(), m_Value()))) { in SimplifyAddWithRemainder()
1185 std::swap(Div, Rem); in SimplifyAddWithRemainder()
1191 MatchDiv(Div, DivOpV, DivOpC, IsSigned) && X == DivOpV && C0 == DivOpC) { in SimplifyAddWithRemainder()
1201 Builder.CreateMul(Div, ConstantInt::get(X->getType(), NewC)), MulXC2); in SimplifyAddWithRemainder()
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| H A D | InstCombineCompares.cpp | 2704 BinaryOperator *Div, in foldICmpDivConstant() argument
2707 Value *X = Div->getOperand(0); in foldICmpDivConstant()
2708 Value *Y = Div->getOperand(1); in foldICmpDivConstant()
2709 Type *Ty = Div->getType(); in foldICmpDivConstant()
2710 bool DivIsSigned = Div->getOpcode() == Instruction::SDiv; in foldICmpDivConstant()
2720 if (Cmp.isEquality() && Div->hasOneUse() && C.isSignBitSet() && in foldICmpDivConstant()
2769 APInt RangeSize = Div->isExact() ? APInt(C2->getBitWidth(), 1) : *C2; in foldICmpDivConstant()
2810 if (Div->isExact()) in foldICmpDivConstant()
4670 Instruction *Div; in foldMultiplicationOverflowCheck() local
4676 m_Instruction(Div)), in foldMultiplicationOverflowCheck()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedThunderX.td | 43 def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt
70 // Div
161 // FP Mul, Div, Sqrt
238 // Div
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| H A D | AArch64SchedA53.td | 48 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
72 // Div
134 // FP Mul, Div, Sqrt
195 // Div
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| H A D | AArch64SchedA55.td | 56 def CortexA55UnitFPDIV : ProcResource<1> { let BufferSize = 0; } // FP Div/SQRT, 64/128
77 // Div
187 // FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
252 // Div
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| H A D | AArch64SchedA510.td | 59 …def CortexA510UnitVMC : ProcResource<1>; // SIMD/FP/SVE multicycle instrs (e.g Div, SQRT, c…
79 // Div
200 // FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
237 // Div
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| H A D | AArch64SchedTSV110.td | 67 // Integer Mul/MAC/Div
96 // FP Div, Sqrt
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVETailPredication.cpp | 327 const SCEV *Div = SE->getUDivExpr( in IsSafeActiveMask() local
331 const SCEV *Sub = SE->getMinusSCEV(SE->getBackedgeTakenCount(L), Div); in IsSafeActiveMask()
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| H A D | ARMScheduleM4.td | 105 // Most FP instructions are single-cycle latency, except MAC's, Div's and Sqrt's.
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| /freebsd/contrib/llvm-project/clang/include/clang/AST/ |
| H A D | CommentHTMLTags.td | 20 def Div : Tag<"div">;
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| H A D | StmtVisitor.h | 128 BINOP_FALLBACK(Mul) BINOP_FALLBACK(Div) BINOP_FALLBACK(Rem) in BINOP_FALLBACK()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCExpr.h | 493 Div, ///< Signed division. enumerator
544 return create(Div, LHS, RHS, Ctx); in createDiv()
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCExpr.cpp | 139 case MCBinaryExpr::Div: OS << '/'; break; in print()
976 case MCBinaryExpr::Div: in evaluateAsRelocatableImpl()
986 if (ABE->getOpcode() == MCBinaryExpr::Div) in evaluateAsRelocatableImpl()
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| H A D | MCWin64EH.cpp | 265 const MCSymbol *RHS, int Div) { in GetSubDivExpr() argument
270 if (Div != 1) in GetSubDivExpr()
271 Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(Div, Context), in GetSubDivExpr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPrepareFunctions.cpp | 358 Value *Div = IRB.CreateUDiv(Mul, UMulFunc->getArg(0)); in buildUMulWithOverflowFunc() local
359 Value *Overflow = IRB.CreateICmpNE(UMulFunc->getArg(0), Div); in buildUMulWithOverflowFunc()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | LoopCacheAnalysis.cpp | 437 const SCEV *Div = SE.getUDivExactExpr(AccessFn, ElemSize); in delinearize() local
438 Subscripts.push_back(Div); in delinearize()
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| H A D | BranchProbabilityInfo.cpp | 501 uint32_t Div = static_cast<uint32_t>( in calcMetadataWeights() local
503 BP[I] = BranchProbability::getRaw(Div); in calcMetadataWeights()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCodeGenPrepare.cpp | 1299 Value *Div = Builder.CreateAdd(IQ, JQ); in expandDivRem24Impl() local
1301 Value *Res = Div; in expandDivRem24Impl()
1304 Value *Rem = Builder.CreateMul(Div, Den); in expandDivRem24Impl()
1621 for (BinaryOperator *Div : Div64ToExpand) { in visitBinaryOperator()
1622 expandDivRem64(*Div); in visitBinaryOperator()
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| H A D | AMDGPUISelLowering.cpp | 1999 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq); in LowerDIVREM24() local
2002 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS); in LowerDIVREM24()
2009 Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize); in LowerDIVREM24()
2013 Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask); in LowerDIVREM24()
2017 return DAG.getMergeValues({ Div, Rem }, DL); in LowerDIVREM24()
2180 SDValue Div = DAG.getSelectCC(DL, C3, Zero, Sel1, Mulhi3, ISD::SETNE); in LowerUDIVREM64() local
2185 Results.push_back(Div); in LowerUDIVREM64()
2333 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS); in LowerSDIVREM() local
2334 SDValue Rem = Div.getValue(1); in LowerSDIVREM()
2336 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign); in LowerSDIVREM()
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