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Searched refs:DestVT (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp183 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
184 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
187 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
190 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
192 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
992 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPExt() local
994 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1071 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPTrunc() local
1073 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp167 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
958 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPExt() local
960 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
976 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPTrunc() local
978 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in SelectFPTrunc()
1269 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1273 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1439 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1441 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in processCallArgs()
1443 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false)) in processCallArgs()
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H A DPPCISelLowering.h1036 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
H A DPPCISelLowering.cpp9241 const SDLoc &dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
9242 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
9243 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
9251 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
9252 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
9253 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
9261 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
9262 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
9263 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
17423 bool PPCTargetLowering::isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp234 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
235 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2827 MVT DestVT; in selectFPToInt() local
2828 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) in selectFPToInt()
2842 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2844 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2847 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2849 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2852 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2860 MVT DestVT; in selectIntToFP() local
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H A DAArch64ISelLowering.cpp12201 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
12208 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
12228 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
12234 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
12239 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
12242 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
12253 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCallingConvEmitter.cpp301 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
302 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n"; in EmitAction()
303 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
315 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
316 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n"; in EmitAction()
317 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp200 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1737 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1741 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectBinaryIntOp()
1953 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1954 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); in ProcessCallArgs()
1956 ArgVT = DestVT; in ProcessCallArgs()
1962 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1963 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true); in ProcessCallArgs()
1965 ArgVT = DestVT; in ProcessCallArgs()
2040 MVT DestVT = RVLocs[0].getValVT(); in FinishCall() local
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H A DARMISelLowering.cpp8276 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
8284 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8300 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8306 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8311 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8314 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8317 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.h190 SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const;
191 SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const;
H A DVECustomDAG.cpp480 SDValue VECustomDAG::getUnpack(EVT DestVT, SDValue Vec, PackElem Part, in getUnpack() argument
487 return DAG.getNode(OC, DL, DestVT, Vec, AVL); in getUnpack()
490 SDValue VECustomDAG::getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, in getPack() argument
495 return DAG.getNode(VEISD::VEC_PACK, DL, DestVT, LoVec, HiVec, AVL); in getPack()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp157 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
869 EVT DestVT = Node->getValueType(0); in LegalizeLoadOps() local
870 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
898 EVT IDestVT = DestVT.changeTypeToInteger(); in LegalizeLoadOps()
905 dl, DestVT, Result); in LegalizeLoadOps()
1774 EVT DestVT, const SDLoc &dl) { in EmitStackConvert() argument
1775 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode()); in EmitStackConvert()
1779 EVT DestVT, const SDLoc &dl, in EmitStackConvert() argument
1782 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); in EmitStackConvert()
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H A DSelectionDAGBuilder.cpp3656 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitICmp() local
3658 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); in visitICmp()
3675 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitFCmp() local
3677 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); in visitFCmp()
3825 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitTrunc() local
3827 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); in visitTrunc()
3835 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitZExt() local
3845 TLI.isSExtCheaperThanZExt(N.getValueType(), DestVT)) { in visitZExt()
3846 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); in visitZExt()
3850 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N, Flags)); in visitZExt()
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H A DLegalizeTypes.cpp895 EVT DestVT) { in CreateStackStoreLoad() argument
902 Align DestAlign = DAG.getReducedAlign(DestVT, /*UseABI=*/false); in CreateStackStoreLoad()
911 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), Align); in CreateStackStoreLoad()
H A DLegalizeVectorTypes.cpp464 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_UnaryOp() local
482 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op, N->getFlags()); in ScalarizeVecRes_UnaryOp()
521 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_ADDRSPACECAST() local
542 return DAG.getAddrSpaceCast(DL, DestVT, Op, SrcAS, DestAS); in ScalarizeVecRes_ADDRSPACECAST()
2559 EVT DestVT = N->getValueType(0); in SplitVecRes_ExtendOp() local
2561 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); in SplitVecRes_ExtendOp()
2577 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) { in SplitVecRes_ExtendOp()
H A DLegalizeTypes.h218 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2684 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
2685 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
2690 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument
2692 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType()
2695 MVT DestVT) { in setOperationPromotedToType() argument
2698 AddPromotedToType(Op, OrigVT, DestVT); in setOperationPromotedToType()
3177 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
3178 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
3195 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
3196 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1019 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable()
1026 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
3354 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP() local
3359 if (DestVT == MVT::f16) in LowerUINT_TO_FP()
3365 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
3368 if (DestVT == MVT::bf16) { in LowerUINT_TO_FP()
3378 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()
3390 if (DestVT == MVT::f32) in LowerUINT_TO_FP()
3393 assert(DestVT == MVT::f64); in LowerUINT_TO_FP()
3399 EVT DestVT = Op.getValueType(); in LowerSINT_TO_FP() local
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H A DAMDGPUISelLowering.h204 bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const override;
H A DSIISelLowering.h291 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
H A DSIISelLowering.cpp979 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
982 DestVT.getScalarType() == MVT::f32 && in isFPExtFoldable()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1108 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() local
1109 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1110 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1111 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); in getVectorTypeBreakdownMVT()
1591 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() local
1592 RegisterVT = DestVT; in getVectorTypeBreakdown()
1594 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1599 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1385 bool isNarrowingProfitable(EVT SrcVT, EVT DestVT) const override;
H A DX86ISelLowering.cpp19127 MVT DestVT = Cast.getSimpleValueType(); in vectorizeExtractedCast() local
19137 MVT ToVT = MVT::getVectorVT(DestVT, NumEltsInXMM); in vectorizeExtractedCast()
19156 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestVT, VCast, in vectorizeExtractedCast()
24516 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT; in LowerEXTEND_VECTOR_INREG() local
24518 unsigned DestWidth = DestVT.getScalarSizeInBits(); in LowerEXTEND_VECTOR_INREG()
24520 unsigned DestElts = DestVT.getVectorNumElements(); in LowerEXTEND_VECTOR_INREG()
24529 Curr = DAG.getBitcast(DestVT, Curr); in LowerEXTEND_VECTOR_INREG()
24532 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()
34362 bool X86TargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable()
34364 return !(SrcVT == MVT::i32 && DestVT == MVT::i16); in isNarrowingProfitable()