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Searched refs:DestVT (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp181 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
182 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
185 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
187 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
188 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
190 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1004 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPExt() local
1006 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1083 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPTrunc() local
1085 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp159 bool PPCEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, Register DestReg,
946 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPExt() local
948 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
964 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPTrunc() local
966 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in SelectFPTrunc()
1257 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1261 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1428 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1430 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in processCallArgs()
1432 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false)) in processCallArgs()
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H A DPPCISelLowering.h1053 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
H A DPPCISelLowering.cpp9391 const SDLoc &dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
9392 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
9393 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
9401 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
9402 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
9403 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
9411 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
9412 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
9413 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
18331 bool PPCTargetLowering::isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp228 Register emitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
229 Register emiti1Ext(Register SrcReg, MVT DestVT, bool isZExt);
2825 MVT DestVT; in selectFPToInt() local
2826 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) in selectFPToInt()
2840 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2842 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2845 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2847 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2850 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2858 MVT DestVT; in selectIntToFP() local
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H A DAArch64ISelLowering.cpp6721 MVT DestVT = Op.getSimpleValueType(); in LowerADDRSPACECAST() local
6735 return DAG.getNode(ISD::SIGN_EXTEND, DL, DestVT, Src, in LowerADDRSPACECAST()
6736 DAG.getTargetConstant(0, DL, DestVT)); in LowerADDRSPACECAST()
6738 return DAG.getNode(ISD::ZERO_EXTEND, DL, DestVT, Src, in LowerADDRSPACECAST()
6739 DAG.getTargetConstant(0, DL, DestVT)); in LowerADDRSPACECAST()
6742 SDValue Ext = DAG.getAnyExtOrTrunc(Src, DL, DestVT); in LowerADDRSPACECAST()
6743 SDValue Trunc = DAG.getZeroExtendInReg(Ext, DL, DestVT); in LowerADDRSPACECAST()
13071 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
13078 DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Src.ShuffleVec, in ReconstructShuffle()
13098 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, DestVT, Src.ShuffleVec, in ReconstructShuffle()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DCallingConvEmitter.cpp283 MVT::SimpleValueType DestVT = getValueType(DestTy); in emitAction() local
284 O << Indent << "LocVT = " << getEnumName(DestVT) << ";\n"; in emitAction()
285 if (MVT(DestVT).isFloatingPoint()) { in emitAction()
297 MVT::SimpleValueType DestVT = getValueType(DestTy); in emitAction() local
298 O << Indent << "LocVT = " << getEnumName(DestVT) << ";\n"; in emitAction()
299 if (MVT(DestVT).isFloatingPoint()) { in emitAction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp225 Register ARMEmitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT, bool isZExt);
1795 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1799 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectBinaryIntOp()
2015 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
2016 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); in ProcessCallArgs()
2018 ArgVT = DestVT; in ProcessCallArgs()
2024 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
2025 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true); in ProcessCallArgs()
2027 ArgVT = DestVT; in ProcessCallArgs()
2102 MVT DestVT = RVLocs[0].getValVT(); in FinishCall() local
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H A DARMISelLowering.cpp8327 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
8335 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8351 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8357 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8362 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8365 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
8368 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.h190 SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const;
191 SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const;
H A DVECustomDAG.cpp480 SDValue VECustomDAG::getUnpack(EVT DestVT, SDValue Vec, PackElem Part, in getUnpack() argument
487 return DAG.getNode(OC, DL, DestVT, Vec, AVL); in getUnpack()
490 SDValue VECustomDAG::getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, in getPack() argument
495 return DAG.getNode(VEISD::VEC_PACK, DL, DestVT, LoVec, HiVec, AVL); in getPack()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp166 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
168 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
886 EVT DestVT = Node->getValueType(0); in LegalizeLoadOps() local
887 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
915 EVT IDestVT = DestVT.changeTypeToInteger(); in LegalizeLoadOps()
922 dl, DestVT, Result); in LegalizeLoadOps()
1838 EVT DestVT, const SDLoc &dl) { in EmitStackConvert() argument
1839 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode()); in EmitStackConvert()
1843 EVT DestVT, const SDLoc &dl, in EmitStackConvert() argument
1846 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); in EmitStackConvert()
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H A DSelectionDAGBuilder.cpp3712 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitICmp() local
3714 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); in visitICmp()
3731 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitFCmp() local
3733 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); in visitFCmp()
3881 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitTrunc() local
3889 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N, Flags)); in visitTrunc()
3897 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); in visitZExt() local
3907 TLI.isSExtCheaperThanZExt(N.getValueType(), DestVT)) { in visitZExt()
3908 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); in visitZExt()
3912 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N, Flags)); in visitZExt()
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H A DLegalizeTypes.cpp898 EVT DestVT) { in CreateStackStoreLoad() argument
905 Align DestAlign = DAG.getReducedAlign(DestVT, /*UseABI=*/false); in CreateStackStoreLoad()
914 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), Align); in CreateStackStoreLoad()
H A DLegalizeVectorTypes.cpp476 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_UnaryOp() local
493 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op, N->getFlags()); in ScalarizeVecRes_UnaryOp()
531 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_ADDRSPACECAST() local
551 return DAG.getAddrSpaceCast(DL, DestVT, Op, SrcAS, DestAS); in ScalarizeVecRes_ADDRSPACECAST()
2698 EVT DestVT = N->getValueType(0); in SplitVecRes_ExtendOp() local
2700 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); in SplitVecRes_ExtendOp()
2716 SrcVT.getScalarSizeInBits() * 2 < DestVT.getScalarSizeInBits()) { in SplitVecRes_ExtendOp()
H A DLegalizeTypes.h218 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1039 EVT DestVT) const { in isNarrowingProfitable()
1057 (!DestVT.isVector() || !Subtarget->hasVOP3PInsts())) { in isNarrowingProfitable()
1059 if (!N->isDivergent() && DestVT.isInteger() && in isNarrowingProfitable()
1060 DestVT.getScalarSizeInBits() > 1 && in isNarrowingProfitable()
1061 DestVT.getScalarSizeInBits() <= 16 && in isNarrowingProfitable()
1078 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
3412 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP() local
3417 if (DestVT == MVT::f16) in LowerUINT_TO_FP()
3423 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
3426 if (DestVT == MVT::bf16) { in LowerUINT_TO_FP()
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H A DAMDGPUISelLowering.h207 bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override;
H A DSIISelLowering.h303 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
H A DSIISelLowering.cpp1045 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
1048 DestVT.getScalarType() == MVT::f32 && in isFPExtFoldable()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1207 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() local
1208 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1209 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1210 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); in getVectorTypeBreakdownMVT()
1690 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() local
1691 RegisterVT = DestVT; in getVectorTypeBreakdown()
1693 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1698 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2777 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
2778 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
2783 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in setOperationPromotedToType() argument
2785 AddPromotedToType(Opc, OrigVT, DestVT); in setOperationPromotedToType()
2788 MVT DestVT) { in setOperationPromotedToType() argument
2791 AddPromotedToType(Op, OrigVT, DestVT); in setOperationPromotedToType()
3275 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
3276 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
3293 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
3294 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1470 bool isNarrowingProfitable(SDNode *N, EVT SrcVT, EVT DestVT) const override;
H A DX86ISelLowering.cpp19832 MVT DestVT = Cast.getSimpleValueType(); in vectorizeExtractedCast() local
19842 MVT ToVT = MVT::getVectorVT(DestVT, NumEltsInXMM); in vectorizeExtractedCast()
19861 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestVT, VCast, in vectorizeExtractedCast()
25370 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT; in LowerEXTEND_VECTOR_INREG() local
25372 unsigned DestWidth = DestVT.getScalarSizeInBits(); in LowerEXTEND_VECTOR_INREG()
25374 unsigned DestElts = DestVT.getVectorNumElements(); in LowerEXTEND_VECTOR_INREG()
25383 Curr = DAG.getBitcast(DestVT, Curr); in LowerEXTEND_VECTOR_INREG()
25386 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr, in LowerEXTEND_VECTOR_INREG()
35614 EVT DestVT) const { in isNarrowingProfitable()
35616 return !(SrcVT == MVT::i32 && DestVT == MVT::i16); in isNarrowingProfitable()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1809 const MVT DestVT = Callee.getValueType().getSimpleVT(); in LowerCall() local
1812 Register DestReg = MRI.createVirtualRegister(TLI.getRegClassFor(DestVT)); in LowerCall()
1814 Callee = DAG.getCopyFromReg(RegCopy, dl, DestReg, DestVT); in LowerCall()