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Searched refs:DemandedElts (Results 1 – 25 of 57) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp72 APInt DemandedElts = in getKnownBits() local
74 return getKnownBits(R, DemandedElts); in getKnownBits()
77 KnownBits GISelKnownBits::getKnownBits(Register R, const APInt &DemandedElts, in getKnownBits() argument
83 computeKnownBitsImpl(R, Known, DemandedElts, Depth); in getKnownBits()
114 const APInt &DemandedElts, in computeKnownBitsMin() argument
117 computeKnownBitsImpl(Src1, Known, DemandedElts, Depth); in computeKnownBitsMin()
124 computeKnownBitsImpl(Src0, Known2, DemandedElts, Depth); in computeKnownBitsMin()
145 const APInt &DemandedElts, in computeKnownBitsImpl() argument
182 if (!DemandedElts) in computeKnownBitsImpl()
189 TL.computeKnownBitsForTargetInstr(*this, R, Known, DemandedElts, MRI, in computeKnownBitsImpl()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DValueTracking.cpp136 const APInt &DemandedElts, in getShuffleDemandedElts() argument
139 assert(DemandedElts == APInt(1,1)); in getShuffleDemandedElts()
140 DemandedLHS = DemandedRHS = DemandedElts; in getShuffleDemandedElts()
147 DemandedElts, DemandedLHS, DemandedRHS); in getShuffleDemandedElts()
150 static void computeKnownBits(const Value *V, const APInt &DemandedElts,
160 APInt DemandedElts = in computeKnownBits() local
162 ::computeKnownBits(V, DemandedElts, Known, Depth, Q); in computeKnownBits()
182 KnownBits llvm::computeKnownBits(const Value *V, const APInt &DemandedElts, in computeKnownBits() argument
187 V, DemandedElts, Depth, in computeKnownBits()
281 static bool isKnownNonZero(const Value *V, const APInt &DemandedElts,
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H A DVectorUtils.cpp313 const APInt &DemandedElts, APInt &DemandedLHS, in getShuffleDemandedElts() argument
318 if (DemandedElts.isZero()) in getShuffleDemandedElts()
332 if (!DemandedElts[I] || (AllowUndefElts && (M < 0))) in getShuffleDemandedElts()
571 const APInt &DemandedElts, in getHorizDemandedEltsForFirstOperand() argument
576 int NumElts = DemandedElts.getBitWidth(); in getHorizDemandedEltsForFirstOperand()
585 if (!DemandedElts[Idx]) in getHorizDemandedEltsForFirstOperand()
1110 APInt DemandedElts = APInt::getAllOnes(VWidth); in possiblyDemandedEltsInMask() local
1114 DemandedElts.clearBit(i); in possiblyDemandedEltsInMask()
1115 return DemandedElts; in possiblyDemandedEltsInMask()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGISelKnownBits.h39 const APInt &DemandedElts,
43 const APInt &DemandedElts, unsigned Depth = 0);
58 const APInt &DemandedElts,
61 unsigned computeNumSignBits(Register R, const APInt &DemandedElts,
67 KnownBits getKnownBits(Register R, const APInt &DemandedElts,
75 /// \return true if 'V & Mask' is known to be zero in DemandedElts. We use
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstCombineIntrinsic.cpp381 APInt DemandedElts = APInt::getAllOnes(VWidth); in trimTrailingZerosInVector() local
395 DemandedElts.clearBit(i); in trimTrailingZerosInVector()
398 return DemandedElts; in trimTrailingZerosInVector()
406 APInt DemandedElts = APInt::getAllOnes(VWidth); in defaultComponentBroadcast() local
424 DemandedElts.clearBit(I); in defaultComponentBroadcast()
427 return DemandedElts; in defaultComponentBroadcast()
432 APInt DemandedElts,
1254 APInt DemandedElts; in instCombineIntrinsic() local
1256 DemandedElts = defaultComponentBroadcast(II.getArgOperand(0)); in instCombineIntrinsic()
1258 DemandedElts = trimTrailingZerosInVector(IC, II.getArgOperand(0), &II); in instCombineIntrinsic()
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H A DAMDGPUISelLowering.h310 const APInt &DemandedElts,
314 unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
320 const APInt &DemandedElts,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp2700 const APInt &DemandedElts, in MaskedValueIsZero() argument
2702 return Mask.isSubsetOf(computeKnownBits(V, DemandedElts, Depth).Zero); in MaskedValueIsZero()
2707 bool SelectionDAG::MaskedVectorIsZero(SDValue V, const APInt &DemandedElts, in MaskedVectorIsZero() argument
2709 return computeKnownBits(V, DemandedElts, Depth).isZero(); in MaskedVectorIsZero()
2719 const APInt &DemandedElts, in computeVectorKnownZeroElements() argument
2725 assert(DemandedElts.getBitWidth() == NumElts && "Unexpected demanded mask."); in computeVectorKnownZeroElements()
2729 if (!DemandedElts[EltIdx]) in computeVectorKnownZeroElements()
2743 bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts, in isSplatValue() argument
2748 assert((!VT.isScalableVector() || DemandedElts.getBitWidth() == 1) && in isSplatValue()
2751 if (!DemandedElts) in isSplatValue()
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H A DTargetLowering.cpp515 const APInt &DemandedElts, in ShrinkDemandedConstant() argument
522 if (DemandedBits.isZero() || DemandedElts.isZero()) in ShrinkDemandedConstant()
526 if (targetShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO)) in ShrinkDemandedConstant()
564 APInt DemandedElts = VT.isVector() in ShrinkDemandedConstant() local
567 return ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO); in ShrinkDemandedConstant()
636 const APInt &DemandedElts, in SimplifyDemandedBits() argument
644 SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO); in SimplifyDemandedBits()
662 APInt DemandedElts = VT.isFixedLengthVector() in SimplifyDemandedBits() local
665 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth, in SimplifyDemandedBits()
671 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, in SimplifyMultipleUseDemandedBits() argument
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp1394 APInt DemandedElts, in SimplifyDemandedVectorElts() argument
1405 assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!"); in SimplifyDemandedVectorElts()
1413 if (DemandedElts.isZero()) { // If nothing is demanded, provide poison. in SimplifyDemandedVectorElts()
1423 if (DemandedElts.isAllOnes()) in SimplifyDemandedVectorElts()
1430 if (!DemandedElts[i]) { // If not demanded, set to poison. in SimplifyDemandedVectorElts()
1466 DemandedElts = EltMask; in SimplifyDemandedVectorElts()
1516 simplifyAndSetOp(I, i, DemandedElts, PoisonEltsOp); in SimplifyDemandedVectorElts()
1534 simplifyAndSetOp(I, 0, DemandedElts, PoisonElts2); in SimplifyDemandedVectorElts()
1541 APInt PreInsertDemandedElts = DemandedElts; in SimplifyDemandedVectorElts()
1562 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) { in SimplifyDemandedVectorElts()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstCombineIntrinsic.cpp2150 APInt DemandedElts = APInt::getLowBitsSet(Width, DemandedWidth); in instCombineIntrinsic() local
2151 return IC.SimplifyDemandedVectorElts(Op, DemandedElts, UndefElts); in instCombineIntrinsic()
3085 APInt DemandedElts = DemandedMask.zextOrTrunc(ArgWidth); in simplifyDemandedUseBitsIntrinsic() local
3087 if (DemandedElts.isZero()) { in simplifyDemandedUseBitsIntrinsic()
3101 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, in simplifyDemandedVectorEltsIntrinsic() argument
3115 if (!DemandedElts[0]) { in simplifyDemandedVectorEltsIntrinsic()
3121 DemandedElts = 1; in simplifyDemandedVectorEltsIntrinsic()
3122 simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); in simplifyDemandedVectorEltsIntrinsic()
3131 simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); in simplifyDemandedVectorEltsIntrinsic()
3134 if (!DemandedElts[0]) { in simplifyDemandedVectorEltsIntrinsic()
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H A DX86ISelLowering.h1204 const APInt &DemandedElts,
1211 const APInt &DemandedElts,
1217 const APInt &DemandedElts,
1222 const APInt &DemandedElts,
1229 const APInt &DemandedElts,
1236 const APInt &DemandedElts,
1242 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
1246 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
1250 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
1253 bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts,
H A DX86TargetTransformInfo.h169 const APInt &DemandedElts,
204 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DValueTracking.h72 KnownBits computeKnownBits(const Value *V, const APInt &DemandedElts,
79 KnownBits computeKnownBits(const Value *V, const APInt &DemandedElts,
510 KnownFPClass computeKnownFPClass(const Value *V, const APInt &DemandedElts,
530 computeKnownFPClass(const Value *V, const APInt &DemandedElts, in computeKnownFPClass() argument
539 computeKnownFPClass(V, DemandedElts, InterestedClasses, Depth, SQ); in computeKnownFPClass()
553 APInt DemandedElts = in computeKnownFPClass() local
555 return computeKnownFPClass(V, DemandedElts, FMF, InterestedClasses, Depth, in computeKnownFPClass()
H A DVectorUtils.h193 const APInt &DemandedElts, APInt &DemandedLHS,
271 const APInt &DemandedElts,
H A DTargetTransformInfo.h685 InstCombiner & IC, IntrinsicInst & II, APInt DemandedElts,
897 const APInt &DemandedElts,
1879 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
1941 const APInt &DemandedElts,
2343 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, in simplifyDemandedVectorEltsIntrinsic() argument
2348 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, in simplifyDemandedVectorEltsIntrinsic()
2484 const APInt &DemandedElts, in getScalarizationOverhead() argument
2487 return Impl.getScalarizationOverhead(Ty, DemandedElts, Insert, Extract, in getScalarizationOverhead()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1926 const APInt &DemandedElts, unsigned Depth = 0) const;
1930 bool MaskedVectorIsZero(SDValue Op, const APInt &DemandedElts,
1939 APInt computeVectorKnownZeroElements(SDValue Op, const APInt &DemandedElts,
1954 KnownBits computeKnownBits(SDValue Op, const APInt &DemandedElts,
2047 unsigned ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
2060 unsigned ComputeMaxSignificantBits(SDValue Op, const APInt &DemandedElts,
2071 bool isGuaranteedNotToBeUndefOrPoison(SDValue Op, const APInt &DemandedElts,
2082 bool isGuaranteedNotToBePoison(SDValue Op, const APInt &DemandedElts,
2084 return isGuaranteedNotToBeUndefOrPoison(Op, DemandedElts,
2097 bool canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
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H A DTargetLowering.h3966 const APInt &DemandedElts,
3978 const APInt &DemandedElts, in targetShrinkDemandedConstant() argument
4005 const APInt &DemandedElts, KnownBits &Known,
4024 const APInt &DemandedElts,
4031 const APInt &DemandedElts,
4044 const APInt &DemandedElts,
4069 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
4086 const APInt &DemandedElts,
4096 const APInt &DemandedElts,
4121 const APInt &DemandedElts,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.h128 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
406 const APInt &DemandedElts,
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h626 const APInt &DemandedElts,
632 const APInt &DemandedElts,
637 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h597 const APInt &DemandedElts,
602 const APInt &DemandedElts,
606 const APInt &DemandedElts,
611 const APInt &DemandedElts,
/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/InstCombine/
H A DInstCombiner.h357 IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
516 SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, APInt &UndefElts,
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h113 const APInt &DemandedElts,
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h198 const APInt &DemandedElts,
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h88 const APInt &DemandedElts,
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h77 const APInt &DemandedElts,

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